Datasheet

MAX2870
23.5MHz to 6000MHz Fractional/
Integer-N Synthesizer/VCO
17Maxim Integrated
Table 6. Register 2 (Address: 010, Default: 00004042
HEX
)
Table 5. Register 1 (Address: 001, Default: 2000FFF9
HEX
) (continued)
BIT LOCATION BIT ID NAME DEFINITION
31 LDS
Lock-Detect
Speed
Lock-detect speed adjustment.
0 = fPFD P 32MHz
1 = fPFD > 32MHz
30:29 SDN[1:0]
Frac-N Noise
Mode
Sets noise mode (See the Low-Spur Mode section.)
00 = Low-noise mode
01 = Reserved
10 = Low-spur mode 1
11 = Low-spur mode 2
28:26 MUX[3:0]
MUX_OUT
Configuration
Sets MUX_OUT pin configuration (MSB bit located register 05).
0000 = Three-state output
0001 = D_VDD
0010 = D_GND
0011 = R-divider output
0100 = N-divider output/2
0101 = Analog lock detect
0110 = Digital lock detect
0111:1011 = Reserved
1100 = Read register 06 MUX_OUT is configured as serial data out.
1101:1111 = Reserved
25 DBR
Reference
Doubler Mode
Sets reference doubler mode.
0 = Disable reference doubler
1 = Enable reference doubler
24 RDIV2
Reference Div2
Mode
Sets reference divider mode.
0 = Disable reference divide-by-2
1 = Enable reference divide-by-2
23:14 R[9:0]
Reference
Divider Mode
Sets reference divide value (R). Double buffered by register 0.
0000000000 = 0 (unused)
0000000001 = 1
-----
1111111111 = 1023
BIT LOCATION BIT ID NAME DEFINITION
14:3 M[11:0]
Modulus Value
(M)
Fractional modulus value used to program f
VCO
. See the Int, Frac, Mod,
and R Counter Relationship section. Double buffered by register 0.
000000000000 = Unused
000000000001 = Unused
000000000010 = 2
-----
111111111111 = 4095
2:0 ADDR[2:0] Address Bits Register address bits