Datasheet

MAX2870
23.5MHz to 6000MHz Fractional/
Integer-N Synthesizer/VCO
18Maxim Integrated
Table 6. Register 2 (Address: 010, Default: 00004042
HEX
) (continued)
BIT LOCATION BIT ID NAME DEFINITION
13 REG4DB Double Buffer
Sets double buffer mode.
0 = Disabled
1 = Enabled
12:9 CP[3:0]
Charge-Pump
Current
Sets charge-pump current in mA (RSET = 5.1kI). Double buffered by
register 0.
0000 = 0.32
0001 = 0.64
0010 = 0.96
0011 = 1.28
0100 = 1.60
0101 = 1.92
0110 = 2.24
0111 = 2.56 [ICP = 1.63/RSET x (1 + CP<3:0>)]
1000 = 2.88
1001 = 3.20
1010 = 3.52
1011 = 3.84
1100 = 4.16
1101 = 4.48
1110 = 4.80
1111 = 5.12
8 LDF
Lock-Detect
Function
Sets lock-detect function.
0 = Frac-N lock detect
1 = Int-N lock detect
7 LDP
Lock-Detect
Precision
Sets lock-detect precision.
0 = 10nS
1 = 6nS
6 PDP
Phase Detector
Polarity
Sets phase detector polarity.
0 = Negative (for use with inverting active loop filters)
1 = Positive (for use with passive loop filers and noninverting
active loop filters)
5 SHDN
Power-Down
Mode
Sets power-down mode.
0 = Normal mode
1 = Device shutdown
4 TRI
Charge-Pump
Three-State
Mode
Sets charge-pump three-state mode.
0 = Disabled
1 = Enabled
3 RST Counter Reset
Sets counter reset mode.
0 = Normal operation
1 = R and N counters reset
2:0 ADDR Address Bits Register address