Datasheet

MAX2870
23.5MHz to 6000MHz Fractional/
Integer-N Synthesizer/VCO
4Maxim Integrated
DIGITAL I/O CHARACTERISTICS
(V
CC_
= +3V to +3.6V, V
GND_
= 0V, T
A
= -40NC to +85NC. Typical values at V
CC
_
= 3.3V, T
A
= +25NC.) (Note 2)
SPI TIMING CHARACTERISTICS
(V
CC_
= +3V to +3.6V, V
GND_
= 0V, T
A
= -40NC to +85NC. Typical values at V
CC
_
= 3.3V, T
A
= +25NC.) (Note 2)
Note 2: Production tested at T
A
= +25NC. Cold and hot are guaranteed by design and characterization.
Note 3: f
REFIN
= 100MHz, phase detector frequency = 25MHz, RF output = 6000MHz.
Register setting: 00780000, 20400061, 20011242, F8010003, 608001FC, 80440005
Note 4: Measured single ended with 27nH to V
CC_RF
into 50I load. Power measured with single output enabled. Unused output
has 27nH to V
CC_RF
with 50I termination.
Note 5: VCO phase noise is measured open loop.
Note 6: Measured at 200kHz using a 50MHz Bliley NV108C19554 OCVCXO with 2MHz loop bandwidth. Register setting
801E0000, 8000FFF9, 80005FC2, 6C10000B, 638E80FC, 400005. EV kit loop filter: C13 = 1500pF, C14 = 33pF, R1 = 0Ω,
R2 = 1100Ω, R0 = 0Ω, C12 = open.
Note 7: 1/f noise contribution to the in-band phase noise is computed by using 1/fnoise + 10log(10kHz/f
OFFSET
) +
20log(f
RF
/1GHz). Register setting: 803A0000,8000FFF9,81005F42,F4000013,6384803C,001500005
Note 8: f
REFIN
= 50MHz; f
PFD
= 25MHz; offset frequency = 10kHz; VCO frequency = 4227MHz, output divide-by-2 enabled.
RFOUT = 2113.5MHz; N = 169; loop BW = 40kHz, CP[3:0] = 1111; integer mode.
Note 9: f
REFIN
= 50MHz; f
PFD
= 50MHz; VCO frequency = 4400MHz, f
RFOUT_
= 4400MHz; loop BW = 65kHz. Register setting:
002C0000, 200303E9, 80005642, 00000133, 638E82FC, 01400005. EV kit loop filter: C13 = 0.1µF, C14 = 0.012µF, R1 =
0Ω, R2 = 120Ω, R0 = 250Ω, C12 = 820pF.
PARAMETER CONDITIONS MIN TYP MAX UNITS
SERIAL INTERFACE INPUTS (CLK, DATA, LE, CE, RFOUT_EN)
Input Logic-Level Low V
IL
0.4 V
Input Logic-Level High V
IH
1.5 V
Input Current I
IH
/I
IL
-1 +1 FA
Input Capacitance 1 pF
SERIAL INTERFACE OUTPUTS (MUX_OUT, LD)
Output Logic-Level Low 0.3mA sink current 0.4 V
Output Logic-Level High 0.3mA source current VCC - 0.4 V
Output Current Level High 0.5 mA
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
CLK Clock Period t
CP
Guaranteed by SCL pulse-width
low and high
50 ns
CLK Pulse-Width Low t
CL
25 ns
CLK Pulse-Width High t
CH
25 ns
LE Setup Time t
LES
20 ns
LE Hold Time t
LEH
10 ns
LE Minimum Pulse-Width High t
LEW
20 ns
Data Setup Time t
DS
25 ns
Data Hold Time t
DH
25 ns
MUX_OUT Setup Time t
MS
10 ns
MUX_OUT Hold Time t
MH
10 ns