Datasheet

ManualsBrandsMAXIM INTEGRATED ManualsLinear ICsMAX2880ETP+

General Description

The MAX2880 is a high-performance phase-locked loop

(PLL) capable of operating in both integer-N and frac-

tional-N modes. Combined with an external reference

oscillator, loop filter, and VCO, the device forms an ultra-

low noise and low-spur frequency synthesizer capable of

accepting RF input frequencies of up to 12.4GHz.

The MAX2880 consists of a high-frequency and low-

noise-phase frequency detector (PFD), precision charge

pump, 10-bit programmable reference counter, 16-bit

integer N counter, and 12-bit variable modulus fractional

modulator.

The MAX2880 is controlled by a 3-wire serial interface

and is compatible with 1.8V control logic. The device is

available in a lead-free, RoHS-compliant, 4mm x 4mm,

20-pin TQFN package, and operates over an extended

-40NC to +85NC temperature range.

Applications

● Microwave Point-to-Point Systems

● Wireless Infrastructure

● Satellite Communications

● Test and Measurement

● RF DAC and ADC Clocks

Benets and Features

● Integer and Fractional-N Modes

● 250MHz to 12.4GHz Broadband RF Input

● Normalized In-Band Noise Floor

• -229dBc/Hz in Integer Mode

• -227dBc/Hz in Fractional Mode

● -10dBm to +5dBm Wide Input Sensitivity

● Low-Noise Phase Frequency Detector

• 105MHz in Fractional Mode

• 140MHz in Integer Mode

● Reference Frequency Up to 205MHz

● Operates from +3.0V to +3.6V Supply

● Cycle Slip Reduction and Fast Lock

● Software and Hardware Shutdown

● Software Lock Detect

● On-Chip Temperature Sensor

● Compatible with +1.8V Control Logic

● Phase Adjustment

Ordering Information appears at end of data sheet.

For related parts and recommended products to use with this part, refer

to www.maximintegrated.com/MAX2880.related.

MUX

÷ 2

PFD

DAT

CLK

12-BIT

FRAC

12-BIT

MOD

COUNTER

SPI AND REGISTERS

REF

PROGRAMMABLE MAIN

MODULATOR

16-BIT

INT

MUX I/O

MUX

RFINN

RFINP

VCP

MAX2880

MUX

÷ 2

REF

DIV

MAX2880 250MHz to 12.4GHz, High-Performance,

Fractional/Integer-N PLL

19-6871; Rev 0; 12/13

Functional Diagram

EVALUATION KIT AVAILABLE

Summary of content (21 pages)

PAGE 1
EVALUATION KIT AVAILABLE MAX2880 250MHz to 12.4GHz, High-Performance, Fractional/Integer-N PLL General Description Benefits and Features ●● Integer and Fractional-N Modes The MAX2880 is a high-performance phase-locked loop (PLL) capable of operating in both integer-N and fractional-N modes. Combined with an external reference oscillator, loop filter, and VCO, the device forms an ultralow noise and low-spur frequency synthesizer capable of accepting RF input frequencies of up to 12.4GHz.
PAGE 2
MAX2880 250MHz to 12.4GHz, High-Performance, Fractional/Integer-N PLL TABLE OF CONTENTS General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Benefits and Features . . . . . . . . . . . . . . . . . . . . . .
PAGE 3
MAX2880 250MHz to 12.4GHz, High-Performance, Fractional/Integer-N PLL LIST OF FIGURES Figure 1. SPI Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Figure 2. Initiating Readback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Figure 3. Reference Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PAGE 4
MAX2880 250MHz to 12.4GHz, High-Performance, Fractional/Integer-N PLL Absolute Maximum Ratings VCC_ to GND_.......................................................-0.3V to +3.9V VCP to GND_........................................................-0.3V to +5.8V CP to GND_.............................................. -0.3V to (VCP + 0.3V) All Other Pins to GND_........................... -0.3V to (VCC_ + 0.3V) RFINP, RFINN.................................................................
PAGE 5
MAX2880 250MHz to 12.4GHz, High-Performance, Fractional/Integer-N PLL AC Electrical Characteristics (continued) (Measured using the MAX2880 Evaluation Kit. VCC_ = 3V to 3.6V, VCP = VCC_ to 5.5V, VGND_ = 0V, fREF = 50MHz, fPFD = 50MHz, fRFINN = 6000MHz, TA = -40°C to +85°C. Typical values measured at VCC_ = 3.3V, VCP = 5V, TA = +25°C, PRFINN = 2dBm, Registers 0 through 4 settings: 303C0000, 00000009, 00008052, 00000BC3, 00000084, unless otherwise noted.) (Note 2) PARAMETER CONDITIONS MIN RSET Range 2.
PAGE 6
MAX2880 250MHz to 12.4GHz, High-Performance, Fractional/Integer-N PLL SPI Timing Characteristics (VCC_ = 3V to 3.6V, VGND_ = 0V, TA = -40°C to +85°C. Typical values at VCC_ = 3.3V, TA = +25°C.
PAGE 7
MAX2880 250MHz to 12.4GHz, High-Performance, Fractional/Integer-N PLL Typical Operating Characteristics (continued) (Measured using the MAX2880 Evaluation Kit. VCC_ = 3.3V, VGND_ = 0V, VCP = 5.0V, CP[3:0]= 1111, fRFINN = 6GHz, fREF = 50MHz, fPFD = 50MHz, TA = +25°C, unless otherwise noted. See Table 1 and Table 2).
PAGE 8
MAX2880 250MHz to 12.4GHz, High-Performance, Fractional/Integer-N PLL Table 1.
PAGE 9
MAX2880 250MHz to 12.4GHz, High-Performance, Fractional/Integer-N PLL LE DATA CLK CE TOP VIEW MUX Pin Configuration 15 14 13 12 11 VCC_RF 16 10 GND VCC_SD 17 9 GND VCP 18 8 REF RSET 19 7 VCC_REF 6 VCC_PLL 2 3 4 RFINP 5 RFINN 1 GND_PLL + GND_SD 20 EP GND_CP CP MAX2880 TQFN 4mm × 4mm Pin Description PIN NAME 1 GND_CP Charge-Pump Ground. Connect to board ground, not to the paddle. FUNCTION 2 GND_SD Sigma Delta Modulator Ground.
PAGE 10
MAX2880 250MHz to 12.4GHz, High-Performance, Fractional/Integer-N PLL Detailed Description Any register can be read back through the MUX pin. The user must first set MUX bits = 0111. Next, write the register to be read, but with the READ bit of that register (the MSB) = 1. If the READ bit is set, the data of bits 30:3 do not matter because they are not latched into the register on a read operation.
PAGE 11
MAX2880 250MHz to 12.4GHz, High-Performance, Fractional/Integer-N PLL Reference Input Integer-N/Fractional-N Modes The reference input signal path also includes optional x2 and ÷2 blocks. When the reference doubler is enabled (DBR = 1), the maximum reference input frequency is lim ited to 100MHz. When the doubler is disabled, the refer ence input frequency is limited to 205MHz. The minimum reference frequency is 10MHz. The minimum R counter divide ratio is 1, and the maximum divide ratio is 1023.
PAGE 12
MAX2880 250MHz to 12.4GHz, High-Performance, Fractional/Integer-N PLL MUX and Lock Detect possible topologies. Once enabled, fast lock is activated after writing to register 0. During this process, the charge pump is automatically increased to its maximum (CP bits = 1111) and the shunt loop filter resistance is reduced to 1/4 of the total resistance when the internal switch shorts the MUX pin to ground. Bits CDIV (register 4, bits 18:7) control the time spent in the wide bandwidth mode.
PAGE 13
MAX2880 250MHz to 12.4GHz, High-Performance, Fractional/Integer-N PLL 20 20 CP MAX2880 R/4 15 MAX2880 R/3 MUX 3R/4 VCO CP 15 MUX 5 RFINN R 5 RFINN VCO Figure 4. Fast-Lock Loop Filter Topology 1 Figure 5. Fast-Lock Loop Filter Topology 2 Phase Adjustment mode, set SDN bits to 00 (register 2, bits 30:29). In the low-spur mode, choose between two possible dithering modes (SDN = 10 or 11) for the optimal spur performance.
PAGE 14
MAX2880 250MHz to 12.4GHz, High-Performance, Fractional/Integer-N PLL Register and Bit Descriptions The operating mode of the MAX2880 is controlled via 5 read/write on-chip registers and 1 read-only register. Defaults are not guaranteed upon power-up and are provided for reference only. All reserved bits should only be written with default values. In shutdown mode, the register values are retained. Table 5.
PAGE 15
MAX2880 250MHz to 12.4GHz, High-Performance, Fractional/Integer-N PLL Table 6. Register 1 (Address: 001, Default: 00000001 Hex) BIT LOCATION BIT ID NAME 31 READ Register Read 0 = Write to register 1 = Read from register 30:27 N[15:12] Integer Division Value Sets Integer part (N divider) of the feedback divider factor. LSBs are located in register 0. All integer values from 16 to 65,535 are allowed for integer mode. Integer values from 19 to 4091 are allowed for fractional mode.
PAGE 16
MAX2880 250MHz to 12.4GHz, High-Performance, Fractional/Integer-N PLL Table 7. Register 2 (Address: 010, Default: 0000FFFA Hex) (continued) BIT LOCATION BIT ID NAME 27:24 CP[3:0] Charge-Pump Current 23:22 Unused Unused 21* RDIV2 Reference Div2 Mode 20* DBR Reference Doubler Mode Sets Reference Doubler Mode 0 = Disable reference doubler 1 = Enable reference doubler Reference Divider Mode Sets Reference Divide Value (R). Double buffered by Register 0. MSBs located in register 1.
PAGE 17
MAX2880 250MHz to 12.4GHz, High-Performance, Fractional/Integer-N PLL Table 8. Register 3 (Address: 011, Default: 00000043 Hex) (continued) BIT LOCATION 13 BIT ID NAME CPOC CP Output Clamp DEFINITION Sets Charge-Pump Output Clamp Mode 0 = Disables clamping of the CP output when the CP is off. 1 = Enables the clamping of the CP output when the CP is off (improved integer-N in-band phase noise). 12:11 CPL[1:0] CP Linearity Sets CP Linearity Mode 00 = Disables the CP linearity mode (integer-N mode).
PAGE 18
MAX2880 250MHz to 12.4GHz, High-Performance, Fractional/Integer-N PLL Table 9.
PAGE 19
MAX2880 250MHz to 12.4GHz, High-Performance, Fractional/Integer-N PLL Typical Application Circuit 15 VCC CP 5.1kΩ C14 R10 R33 C13 17 9 MAX2880 18 8 EP 19 7 + 20 1 6 2 3 4 5 100pF C15 GND GND REF VCC VCC VCC_REF VCC_PLL 100pF 51Ω VCO www.maximintegrated.
PAGE 20
MAX2880 250MHz to 12.4GHz, High-Performance, Fractional/Integer-N PLL Package Information Ordering Information PART TEMP RANGE PIN-PACKAGE MAX2880ETP+ -40°C to +85°C 20 TQFN-EP* +Denotes lead(Pb)-free/RoHS-compliant package. *EP = Exposed pad. www.maximintegrated.com For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only.
PAGE 21
MAX2880 250MHz to 12.4GHz, High-Performance, Fractional/Integer-N PLL Revision History REVISION NUMBER REVISION DATE 0 12/13 DESCRIPTION Initial release PAGES CHANGED — For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim Integrated’s website at www.maximintegrated.com. Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product.