Datasheet

Reference Input
The reference input stage is configured as a CMOS
inverter with shunt resistance from input to output. In shut-
down mode this input is set to high impedance to prevent
loading of the reference source.
The reference input signal path also includes optional x2
and ÷2 blocks. When the reference doubler is enabled
(DBR = 1), the maximum reference input frequency is lim-
ited to 100MHz. When the doubler is disabled, the refer-
ence input frequency is limited to 205MHz. The minimum
reference frequency is 10MHz. The minimum R counter
divide ratio is 1, and the maximum divide ratio is 1023.
Int, Frac, Mod, and R Counter Relationship
The phase-detector frequency is determined as follows:
f
PFD
= f
REF
x [(1 + DBR)/(R x (1 + RDIV2))]
f
REF
represents the external reference input frequency.
DBR (register 2, bit 20) sets the f
REF
input frequency
doubler mode (0 or 1). RDIV2 (register 2, bit 21) sets the
f
REF
divide-by-2 mode (0 or 1). R (register 2, bits 19:15)
is the value of the 5-bit programmable reference counter
(1 to 31). The maximum f
PFD
is 105MHz for Fractional-N
and 140MHz for Integer-N. The R-divider can be held in
reset when RST (register 3, bit 3) = 1.
The VCO frequency is determined as follows:
f
VCO
= f
PFD
x (N + F/M) x (PRE + 1)
N is the value of the 16-bit N counter (16 to 65535), pro-
grammable through bits 30:27 (MSBs) of register 1 and
bits 26:15 of register 0 (LSBs). M is the fractional modu-
lus value (2 to 4095), programmable through bits 14:3 of
register 2. F is the fractional division value (0 to MOD - 1),
programmable through bits 14:3 of register 0. In fraction-
al-N mode, the minimum N value is 19 and maximum N
value is 4091. The N counter is held in reset when RST
= 1 (register 3, bit 3). PRE is RF input prescaler control
where 0 = divide-by-1, and 1 = divide-by-2 (register 1, bit
25). If the RF input frequency is above 6.2GHz, then set
PRE = 1.
Integer-N/Fractional-N Modes
Integer-N mode is selected by setting bit INT = 1 (reg-
ister 3, bit 10). When operating in integer-N mode, it is
also necessary to set bit Lock Detect Function, LDF = 1
(register 3, bit 9) to set the lock detect to integer-N mode.
The device’s fractional-N mode is selected by setting bit
INT = 0 (register 3, bit 10). Additionally, set bit LDF = 0
(register 3, bit 9) for fractional-N lock-detect mode.
If the device is in fractional-N mode, it will remain in frac-
tional-N mode when fractional division value F = 0, which
can result in unwanted spurs. To avoid this condition, the
device can automatically switch to integer-N mode when
F = 0 if the bit F01 = 1 (register 4, bit 29).
Phase Detector and Charge Pump
The device’s charge-pump current is determined by the
value of the resistor from pin RSET to ground and the
value of bits CP (register 2, bits 27:24) as follows:
I
CP
= 1.63/R
SET
x (1 + CP)
When operating in the fractional-N mode, the charge-
pump linearity (CPL) bits can be adjusted by the user to
optimize in-band noise and spur levels. In the integer-N
mode, CPL must be set to 0. If lower noise operation in
integer-N mode is desired, set the charge-pump output
clamp bit CPOC = 1 (register 3, bit 13) to prevent leak-
age current into the loop lter. In fractional-N mode, set
CPOC = 0..
The charge-pump output can be put into high-impedance
mode when TRI = 1 (register 3, bit 4). The output is in
normal mode when TRI = 0.
The phase detector polarity can be changed if an active
inverting loop filter topology is used. For noninverting loop
filters, set PDP = 1 (register 3, bit 6). For inverting loop
filters, set PDP = 0.
Figure 3. Reference Input
REF_IN
X2
DIVIDE-BY-2R COUNTER
MUXMUX TO PFD
MAX2880 250MHz to 12.4GHz, High-Performance,
Fractional/Integer-N PLL
www.maximintegrated.com
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