Datasheet

MUX and Lock Detect
MUX is a multipurpose test output for observing various
internal functions of the MAX2880. MUX can also be
configured as serial data output. MUX bits (register 0, bit
30:27) are used to select the desired MUX signal (see
Table 5).
The digital lock detect is dependent on the mode of the
synthesizer. In fractional-N mode set LDF = 0, and in
integer-N mode set LDF = 1. To set the accuracy of the
digital lock detect, see Table 3 and Table 4.
Cycle Slip Reduction
Cycle slip reduction is one of two available methods to
improve lock time. It is enabled by setting CSR bit (regis-
ter 2, bit 28) to 1. In this mode, the charge pump must be
set for its minimum value.
Fast-Lock
Fast-lock is the other method available for improving lock
time by temporarily increasing the loop bandwidth at the
start of the locking cycle. It is enabled by setting the CDM
bits to 01 (register 4, bits 20:19). In addition, the charge-
pump current has to be set to CP = 0000 (register 2,
bits 27:24), MUX bits configured to 1100 (register 0, bits
30:27), and the shunt resistive portion of the loop filter has
to be segmented into two parts, where one resistor is 1/4
of the total resistance, and the other resistor is 3/4 of the
total resistance. Figure 4 and Figure 5 illustrate the two
possible topologies. Once enabled, fast lock is activated
after writing to register 0. During this process, the charge
pump is automatically increased to its maximum (CP bits
= 1111) and the shunt loop filter resistance is reduced to
1/4 of the total resistance when the internal switch shorts
the MUX pin to ground. Bits CDIV (register 4, bits 18:7)
control the time spent in the wide bandwidth mode. The
time spent in the fast lock is:
t = CDIV/f
PFD
The time should be set long enough to allow the loop to
settle before switching back to the lower loop bandwidth.
RF Inputs
The differential RF inputs are connected to a high-imped-
ance input buffer which drives a demultiplexer for select-
ing between two RF input frequency ranges: 250MHz to
6.2GHz and 6.2GHz to 12.4GHz. When the RF input fre-
quency is 250MHz to 6.2GHz, the fixed divide-by-2 pres-
caler is bypassed by setting bit PRE to 0. When the RF
input frequency is 6.2GHz to 12.4GHz, the fixed divide-
by-2 path is selected by setting PRE to 1. The supported
input power range is -10dBm to +5dBm. For single-ended
operation, terminate the unused RF input to GND through
a 100pF capacitor.
Since the RF input of the device is high impedance, a
DC isolated external shunt resistor is used to provide
the 50Ω input impedance for the system (see the Typical
Application Circuit).
Table 3. Fractional-N Digital Lock-Detect Settings
Table 4. Integer-N Digital Lock-Detect Settings
PFD FREQUENCY
(MHz)
LDS LDP
LOCKED UP/DOWN
TIME SKEW (ns)
NUMBER OF LOCKED
CYCLES TO SET LD
TIME SKEW TO
UNSET LD (ns)
≤ 32 0 0 10 40 15
≤ 32 0 1 6 40 15
> 32 1 X 4 40 4
PFD FREQUENCY
(MHz)
LDS LDP
LOCKED UP/DOWN
TIME SKEW (ns)
NUMBER OF LOCKED
CYCLES TO SET LD
TIME SKEW TO
UNSET LD (ns)
≤ 32 0 0 10 5 15
≤ 32 0 1 6 5 15
> 32 1 X 4 5 4
MAX2880 250MHz to 12.4GHz, High-Performance,
Fractional/Integer-N PLL
www.maximintegrated.com
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