Datasheet

Phase Adjustment
After achieving lock, the phase of the RF output can be
changed in increments of P (register 1, bits 14:3)/M (reg-
ister 2, bits 14:3) x 360°.
When aligning the phase of multiple devices, connect
their MUX pins together and do the following:
1) Force the voltage on the MUX pins to V
IL
.
2) Set MUX = 1000.
3) Program the MAX2880s for the desired frequency and
allow them to lock.
4) Force the voltage on the MUX pins to V
IH
. This resets
the MAX2880s so they are synchronous.
5) Set P (register 1, bits 14:3) for the desired amount of
phase shift for each part.
6) Set CDM bits (register 4, bits 20:19) = 10. This enables
the phase shift.
7) Reset CDM = 00.
Fractional Modes
The MAX2880 offers three modes for the sigma-delta
modulator. Low noise mode offers lower in-band noise at
the expense of spurs, and the low-spur modes offer lower
spurs at the expense of noise. To operate in low noise
mode, set SDN bits to 00 (register 2, bits 30:29). In the
low-spur mode, choose between two possible dithering
modes (SDN = 10 or 11) for the optimal spur performance.
Temperature Sensor
The device is equipped with an on-chip temperature sen-
sor and 7-bit ADC.
To read the digitized output of the temperature sensor:
1) Set CDM = 11 to enable the ADC clock.
2) Set CDIV = f
PFD
/100kHz. If the result is not an integer,
then round down to the nearest integer.
3) Set ADCM (register 4, bits 6:4) = 001 for temperature
sensor mode.
4) Set ADCS (register 4, bit 3) = 1 to start the ADC.
5) Wait at least 100µs for the ADC to convert the tem-
perature.
6) Set MUX = 0111 to read the temperature out of the
MUX pin.
7) Read back register 6. Bits 9:3 are the ADC digitized
value.
The temperature can be converted as:
t = -1.8 x ADC + 129°C
Figure 4. Fast-Lock Loop Filter Topology 1 Figure 5. Fast-Lock Loop Filter Topology 2
VCO
20
15
5
CP
MAX2880
RFINN
R/4
3R/4
MUX
VCO
20
15
5
CP
MUX
RFINN
R
R/3
MAX2880
MAX2880 250MHz to 12.4GHz, High-Performance,
Fractional/Integer-N PLL
www.maximintegrated.com
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