Datasheet
Register and Bit Descriptions
The operating mode of the MAX2880 is controlled via 5
read/write on-chip registers and 1 read-only register.
Defaults are not guaranteed upon power-up and are pro-
vided for reference only. All reserved bits should only be
written with default values. In shutdown mode, the regis-
ter values are retained.
Table 5. Register 0 (Address: 000, Default: 383C0000 Hex)
BIT LOCATION BIT ID NAME DEFINITION
31 READ READ
0 = Write to register
1 = Read from register
30:27 MUX[3:0] MUX Mode
Sets MUX Pin Conguration
0000 = High-Impedance Output
0001 = D_VDD
0010 = D_GND
0011 = R Divider Output
0100 = N Divider Output
0101 = Analog Lock Detect
0110 = Digital Lock Detect
0111 = SPI Output
1000 = SYNC input
1001 = Reserved
1010 = Reserved
1011 = Reserved
1100 = Fast Lock
1101 = R Divider/2
1110 = N Divider/2
1111 = Reserved
26:15 N[11:0]
Integer
Division Value
Sets integer part (N divider) of the feedback divider factor. MSBs are located
in register 1. All integer values from 16 to 65,535 are allowed for integer
mode. Integer values from 19 to 4091 are allowed for fractional mode.
14:3 F[11:0]
Fractional
Division Value
Sets Fractional Value. Allowed F values are 0 to M-1.
000000000000 = 0 (see F01 bit description)
000000000001 = 1
----
111111111110 = 4094
111111111111 = 4095
2:0 ADDR[2:0] Address Bits Register address bits
MAX2880 250MHz to 12.4GHz, High-Performance,
Fractional/Integer-N PLL
www.maximintegrated.com
Maxim Integrated
│
14