Datasheet

Table 6. Register 1 (Address: 001, Default: 00000001 Hex)
Table 7. Register 2 (Address: 010, Default: 0000FFFA Hex)
*Bits double buffered by Register 0.
BIT LOCATION BIT ID NAME DEFINITION
31 READ Register Read
0 = Write to register
1 = Read from register
30:27 N[15:12]
Integer
Division Value
Sets Integer part (N divider) of the feedback divider factor. LSBs are located
in register 0. All integer values from 16 to 65,535 are allowed for integer
mode. Integer values from 19 to 4091 are allowed for fractional mode.
26 Unused Unused Set to 0
25 PRE
RF Input
Prescaler
Sets RF Input prescaler to divide-by-1 or divide-by-2
0 = Divide-by-1 (250MHz to 6.2GHz)
1 = Divide-by-2 (6.2GHz to 12.4GHz)
24:20 Unused Unused Set to all 0’s.
19:15* R[9:5]
Reference
Divider Mode
Sets Reference Divide Value (R). LSBs located in register 2.
0000000000 = 0 (Unused)
0000000001 = 1
-----
1111111111 = 1023
14:3 P[11:0] Phase Value
Sets Phase Value.
See the Phase Adjustment section
000000000000 = 0
000000000001 = 1
-----
111111111111 = 4095
2:0 ADDR[2:0] Address Bits Register address bits
BIT LOCATION BIT ID NAME DEFINITION
31 READ Register Read
0 = Write to register
1 = Read from register
30:29 SDN[1:0]
Fractional-N
Modes
Sets Noise Mode (see the Fractional Modes section under the Detailed
Description):
00 = Low-Noise Mode
01 = Reserved
10 = Low-Spur Mode 1
11 = Low-Spur Mode 2
28 CSR
Cycle Slip
Reduction
0 = Cycle Slip Reduction disabled
1 = Cycle Slip Reduction enabled
MAX2880 250MHz to 12.4GHz, High-Performance,
Fractional/Integer-N PLL
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