Datasheet

Table 8. Register 3 (Address: 011, Default: 00000043 Hex)
Table 7. Register 2 (Address: 010, Default: 0000FFFA Hex) (continued)
*Bits double buffered by Register 0.
BIT LOCATION BIT ID NAME DEFINITION
27:24 CP[3:0]
Charge-Pump
Current
Sets Charge-Pump Current
[ICP = 1.63/RSET x (1 + CP[3:0])]
23:22 Unused Unused Factory Use Only, set to 00.
21* RDIV2
Reference
Div2 Mode
Sets Reference Divider Mode
0 = Disable reference divide by 2
1 = Enable reference divide by 2
20* DBR
Reference
Doubler Mode
Sets Reference Doubler Mode
0 = Disable reference doubler
1 = Enable reference doubler
19:15* R[4:0]
Reference
Divider Mode
Sets Reference Divide Value (R). Double buffered by Register 0. MSBs
located in register 1.
0000000000 = 0 (Unused)
0000000001 = 1
-----
1111111111 = 1023
14:3* M[11:0] Modulus Value
Fractional Modulus value used to program f
VCO
. See the Int, Frac, Mod, and
R Counter Relationship section. Double buffered by register 0.
000000000000 = Unused
000000000001 = Unused
000000000010 = 2
-----
111111111111 = 4095
2:0 ADDR Address Bits Register address
BIT LOCATION BIT ID NAME DEFINITION
31 READ Register Read
0 = Write to register
1 = Read from register
30:18 Unused Unused Write to all 0’s
17 F01 F01
Sets integer mode for F =0.
0 = If F[11:0] = 0, then fractional-N mode is set
1 = If F[11:0] = 0, then integer-N mode is auto set
16:15 CPT[1:0]
Charge-Pump
Test
Sets Charge-Pump Test Modes
00 = Normal mode
01 = Reserved
10 = Force CP into source mode
11 = Force CP into Sink mode
14 RSTSD
Sigma Delta
Reset
0 = Reset Sigma Delta Modulator to known value after each write to register 0
1 = Do not reset Sigma Delta Modulator to known value after each write to
register 0
MAX2880 250MHz to 12.4GHz, High-Performance,
Fractional/Integer-N PLL
www.maximintegrated.com
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