Datasheet

Table 8. Register 3 (Address: 011, Default: 00000043 Hex) (continued)
BIT LOCATION BIT ID NAME DEFINITION
13 CPOC
CP Output
Clamp
Sets Charge-Pump Output Clamp Mode
0 = Disables clamping of the CP output when the CP is off.
1 = Enables the clamping of the CP output when the CP is off (improved
integer-N in-band phase noise).
12:11 CPL[1:0] CP Linearity
Sets CP Linearity Mode
00 = Disables the CP linearity mode (integer-N mode).
01 = Enables the CP linearity mode (Fractional-N mode)
10 = Enables the CP linearity mode (Fractional-N mode)
11 = Enables the CP linearity mode (Fractional-N mode)
10 INT Integer Mode
Controls Synthesizer Integer or Fractional-N Mode
0 = Fractional-N mode
1 = Integer mode
9 LDF
Lock Detect
Function
Sets Lock Detect Function
0 = Fractional-N lock detect
1 = Integer-N lock detect
8 LDS
Lock Detect
Speed
Lock Detect Speed Adjustment
0 = f
PFD
≤ 32MHz
1 = f
PFD
> 32MHz
7 LDP
Lock Detect
Precision
Sets Lock Detect Precision
0 = 10ns
1 = 6ns
6 PDP
Phase Detector
Polarity
Sets Phase Detector Polarity
0 = Negative (for use with inverting active loop lters)
1 = Positive (for use with passive loop lers and noninverting
active loop lters)
5 SHDN
Shutdown
Mode
Sets Power-Down Mode
0 = Normal mode
1 = Device shutdown
4 TRI
Charge-
Pump High-
Impedance
Mode
Sets Charge-Pump High-Impedance Mode
0 = Disabled
1 = Enabled
3 RST Counter Reset
Sets Counter Reset Mode
0 = Normal operation
1 = R and N counters reset
2:0 ADDR[2:0] Address Bits Register address
MAX2880 250MHz to 12.4GHz, High-Performance,
Fractional/Integer-N PLL
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