EVALUATION KIT AVAILABLE MAX3107 SPI/I2C UART with 128-Word FIFOs General Description The MAX3107 is an advanced universal asynchronous receiver-transmitter (UART) with 128 words each of receive and transmit first-in/first-out (FIFO) that can be controlled through I2C or high-speed SPI. The 2x and 4x rate modes allow a maximum of 24Mbps data rates.
MAX3107 SPI/I2C UART with 128-Word FIFOs TABLE OF CONTENTS Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Package Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MAX3107 SPI/I2C UART with 128-Word FIFOs TABLE OF CONTENTS (continued) Power-Up and IRQ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Interrupt Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Interrupt Enabling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MAX3107 SPI/I2C UART with 128-Word FIFOs LIST OF FIGURES Figure 1. I2C Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Figure 2. SPI Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Figure 3. Transmit FIFO Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MAX3107 SPI/I2C UART with 128-Word FIFOs LIST OF REGISTERS RHR—Receiver Hold Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 THR—Transmit Hold Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 IRQEn—IRQ Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MAX3107 SPI/I2C UART with 128-Word FIFOs ABSOLUTE MAXIMUM RATINGS (Voltages referenced to AGND.) VL, VA, VEXT, XIN................................................. -0.3V to +4.0V V18, XOUT................................................... -0.3V to (VA + 0.3V) RST, IRQ, DIN/A1, CS/A0, SCLK/SCL, DOUT/SDA, LDOEN, I2C/SPI................... -0.3V to (VL + 0.3V) TX, RX, RTS/CLKOUT, CTS, GPIO_........ -0.3V to (VEXT + 0.3V) DGND................................................................... -0.3V to +0.
MAX3107 SPI/I2C UART with 128-Word FIFOs DC ELECTRICAL CHARACTERISTICS (continued) (VA = +2.35V to +3.6V, VL = +1.71V to +3.6V, VEXT = +1.71V to +3.6V, TA = -40NC to +85NC, unless otherwise noted. Typical values are at VA = +2.8V, VL = +1.8V, VEXT = +2.5V, TA = +25NC.) (Note 2) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS ILOAD = -3mA, VL > 2V 0.4 V ILOAD = -3mA, VL < 2V 0.
MAX3107 SPI/I2C UART with 128-Word FIFOs DC ELECTRICAL CHARACTERISTICS (continued) (VA = +2.35V to +3.6V, VL = +1.71V to +3.6V, VEXT = +1.71V to +3.6V, TA = -40NC to +85NC, unless otherwise noted. Typical values are at VA = +2.8V, VL = +1.8V, VEXT = +2.5V, TA = +25NC.) (Note 2) PARAMETER SYMBOL CONDITIONS Input Low Voltage VIL Configured as an input Input High Voltage VIH Configured as an input Pulldown Current IPD GPIO_ = VEXT Input Capacitance CIN_IUART MIN TYP MAX UNITS 0.4 V 2.
MAX3107 SPI/I2C UART with 128-Word FIFOs AC ELECTRICAL CHARACTERISTICS (continued) (VA = +2.35V to +3.6V, VL = +1.71V to +3.6V, VEXT = +1.71V to +3.6V, TA = -40NC to +85NC, unless otherwise noted. Typical values are at VA = +2.8V, VL = +1.8V, VEXT = +2.5V, TA = +25NC.
MAX3107 SPI/I2C UART with 128-Word FIFOs Test Circuits/Timing Diagrams START CONDITION (S) REPEATED START CONDITION (Sr) tR STOP CONDITION (P) tF SDA tBUF tHD:DAT tHD:STA tHD:STA tSU:DAT tSU:STO tSU:STA SCL tHIGH tR tF START CONDITION (S) tLOW Figure 1. I2C Timing Diagram CS tCSH tCSS tCL tCH tCSH SCLK tDS tDH DIN tDO DOUT Figure 2.
MAX3107 SPI/I2C UART with 128-Word FIFOs Typical Operating Characteristics (VA = 2.5V, VL = 2.5V, VEXT = 2.5V, LDOEN = VL, TA = +25NC, unless otherwise noted.) IA SUPPLY CURRENT vs. VA VOLTAGE (EXTERNAL CLOCK, PLL DISABLED) LDOEN = VL 3.4 LDOEN = VL 3.2 80 IA (mA) 60 3.0 LDOEN = AGND 1.8V APPLIED TO V18 2.8 2.6 40 LDOEN = AGND 1.8V APPLIED TO V18 20 2.4 EXTERNAL 614kHz CLOCK BAUD RATE = 115kbps 6x PLL MULT.FACTOR 2.2 0 2.0 2.35 2.60 2.85 3.10 3.35 3.60 2.35 2.60 2.
MAX3107 SPI/I2C UART with 128-Word FIFOs GPIO3 GPIO2 GPIO1 18 RTS/CLKOUT RX TOP VIEW CTS Pin Configurations 17 16 15 14 13 TX 19 12 GPIO0 VEXT 20 11 DGND XOUT 21 10 VL MAX3107 XIN 22 AGND 23 *EP + 5 6 CS/A0 4 SCLK/SCL 3 DOUT/SDA I2C/SPI 2 V18 1 LDOEN VA 24 TQFN (3.5mm × 3.
MAX3107 SPI/I2C UART with 128-Word FIFOs Pin Descriptions (continued) PIN NAME FUNCTION TQFN-EP SSOP 7 10 DIN/A1 8 11 IRQ Active-Low Interrupt Open-Drain Output. IRQ is asserted when an interrupt is pending. 9 12 RST Active-Low Reset Input. Drive RST low to force the UART into hardware reset mode. In hardware reset mode, the oscillator and the internal PLL are shut down; there is no clock activity. 10 13 VL Digital Interface Logic-Level Supply.
MAX3107 SPI/I2C UART with 128-Word FIFOs Register Map (All default reset values are 0x00, unless otherwise noted. All registers are R/W, unless otherwise noted.
MAX3107 SPI/I2C UART with 128-Word FIFOs Detailed Description The MAX3107 UART is a bridge between an SPI/ MICROWIRE™ or I2C microprocessor bus and an asynchronous serial-data communication link, such as RS-485, RS-232, or IrDA. The MAX3107 contains an advanced UART, a fractional baud-rate generator, and four GPIOs. The MAX3107 is configured and monitored, and data is written and read from 8-bit registers through SPI or I2C. These registers are organized by related function as shown in the Register Map.
MAX3107 SPI/I2C UART with 128-Word FIFOs LSB RECEIVED DATA START MSB D0 D1 D2 D3 D4 D5 D6 D7 PARITY STOP STOP MIDBIT SAMPLING Figure 4. Receive Data Format ONE BIT PERIOD RX BAUD BLOCK A 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 MAJORITY CENTER SAMPLER Figure 5. Midbit Sampling To halt transmission, set MODE1[1]: TxDisabl to 1. After MODE1[1] is set, the transmitter completes transmission of the current character and then ceases transmission.
MAX3107 SPI/I2C UART with 128-Word FIFOs RECEIVER LSR[1] ISR[3] OVERRUN TRIGGER WORD RECEIVED DATA RX ERROR 128 PLL and Predivider The internal predivider and PLL allow for a wide range of external clock frequencies and baud rates. The PLL can be configured to multiply the input clock rate by a factor of 6, 48, 96, or 144 through PLLConfig[7:6]. The predivider, located between the input clock and the PLL, allows division of the input clock by a factor between 1 and 63 by writing to PLLConfig[5:0].
MAX3107 SPI/I2C UART with 128-Word FIFOs DIV can be a maximum of 16 bits wide and is programmed into the 2-byte-wide registers DIVMSB and DIVLSB. The minimum allowed for DIVLSB is 1. The fractional portion of the divisor, FRACT, is a 4-bit nibble, which is programmed into BRGConfig[3:0]. The maximum value is 15, allowing the divisor to be programmed with a resolution of 0.0625. FRACT is calculated as: FRACT = ROUND(16 x (D-DIV)) The following is an example of calculating the divisor.
MAX3107 SPI/I2C UART with 128-Word FIFOs Multidrop Mode In multidrop mode, also known as 9-bit mode, the word length is 8 bits and a 9th bit is used for distinguishing between an address and a data word. Multidrop mode is enabled through MODE2[6]: MultiDrop. Parity checking is disabled and an SpclCharInt[5]: MultiDropInt interrupt is generated when an address (9th bit set) is received. It is up to the host processor to filter out the data intended for its address.
MAX3107 SPI/I2C UART with 128-Word FIFOs RTS/CLKOUT SETUP HOLD TX FIRST CHARACTER LAST CHARACTER Figure 10. Setup and Hold Times in Auto Transceiver Direction Control Echo Suppression The MAX3107 can suppress echoed data, sometimes found in half-duplex communication (e.g., RS-485 and IrDA). If the transceiver’s receiver is not turned off while the transceiver is transmitting, copies (echoes) are received by the UART.
MAX3107 SPI/I2C UART with 128-Word FIFOs STOP BIT TX HOLD DELAY DI TO RO PROPAGATION DELAY RX RTS/CLKOUT Figure 12. Echo Suppression Timing RESUME are programmed in FlowLvl. With differing HALT and RESUME levels, hysteresis can be defined for the RTS/CLKOUT transitions. When the RxFIFO fill level reaches the HALT level (FlowLvl[3:0]), the MAX3107 deasserts RTS/CLKOUT. RTS/CLKOUT remains deasserted until the RxFIFO is emptied and the number of words falls to the RESUME level.
MAX3107 SPI/I2C UART with 128-Word FIFOs Transmitter Flow Control If auto transmitter control (FlowCtrl[5:4]) is enabled, the receiver compares all received words with the XOFF and XON characters. If a XOFF is received, the MAX3107 halts its transmitter from sending further data. The receiver is not affected and continues reception. Upon receiving an XON, the transmitter restarts sending data.
MAX3107 SPI/I2C UART with 128-Word FIFOs Interrupt Structure enable register bit. These are the IRQEn, LSRIntEn, SpclChrIntEn and STSIntEn registers. The structure of the interrupt is shown in Figure 13. There are four interrupt source registers: ISR, LSR, STSInt, and SpclCharInt. The interrupt sources are divided into toplevel and low-level interrupts. The top-level interrupts typically occur more often and can be read out directly through the ISR.
MAX3107 SPI/I2C UART with 128-Word FIFOs THR—Transmit Hold Register ADDRESS: MODE: 0x00 W BIT 7 6 5 4 3 2 1 0 NAME TData7 TData6 TData5 TData4 TData3 TData2 TData1 TData0 Bits 7–0: TData[7:0] The THR is the register that the host controller writes data to for subsequent UART transmission. This data is deposited in the transmit FIFO. THR[0] is the LSB. It is the first data bit of the serial-data word that the transmitter sends out, right after the START bit.
MAX3107 SPI/I2C UART with 128-Word FIFOs Bit 0: LSRErrlEn The LSRErrIEn bit enables IRQ interrupt generation when the LSRErrInt interrupt bit is set in the ISR[0]. Set LSRErrIEn low to disable IRQ generation from LSRErrInt. ISR—Interrupt Status Register ADDRESS: MODE: 0x02 COR BIT 7 6 5 4 3 2 1 0 NAME CTSInt RxEmptyInt TxEmptyInt TFifoTrigInt RFifoTrigInt STSInt SpCharInt LSRErrInt RESET 0 1 1 0 0 0 0 0 The ISR provides an overview of all interrupts generated in the MAX3107.
MAX3107 SPI/I2C UART with 128-Word FIFOs LSRIntEn—Line Status Register Interrupt Enable ADDRESS: MODE: 0x03 R/W BIT 7 6 5 4 3 2 1 0 NAME — — NoiseIntEn RBreakIEn FrameErrIEn ParityIEn ROverrIEn RTimoutIEn RESET 0 0 0 0 0 0 0 0 The LSRIntEn allows routing of LSR interrupt bits to the ISR[0]. Bits 7 and 6: No Function Bit 5: NoiseIntEn Set the NoiseIntEn bit high to enable routing the RxNoise interrupt to LSR[0]. If NoiseIntEn is set low, RxNoise is not routed to LSR[0].
MAX3107 SPI/I2C UART with 128-Word FIFOs LSR—Line Status Register ADDRESS: MODE: 0x04 R BIT 7 6 5 4 3 2 1 0 NAME CTSbit — RxNoise RxBreak FrameErr RxParityErr RxOverrun RTimeout RESET X 0 0 0 0 0 0 0 The LSR shows all errors related to the word previously read out of the RxFIFO. The LSR bits are not cleared upon a read; these bits stay set until the character with errors is read out of the RHR. The LSR also reflects the current state of the CTS input.
MAX3107 SPI/I2C UART with 128-Word FIFOs Bit 0: RTimeout The RTimeout bit indicates that stale data is present in the receive FIFO. RTimeout is set when the youngest character resides in the RxFIFO for longer than the period programmed into the RxTimeOut register. The timeout counter restarts when at least one character is read out of the RxFIFO or a new character is received by the RxFIFO. If the value in RxTimeOut is zero, RTimeout is disabled.
MAX3107 SPI/I2C UART with 128-Word FIFOs SpclCharInt—Special Character Interrupt Register ADDRESS: MODE: 0x06 COR BIT 7 6 5 4 3 2 1 0 NAME — — MultiDropInt BREAKInt XOFF2Int XOFF1Int XON2Int XON1Int RESET 0 0 0 0 0 0 0 0 Bits 7 and 6: No Function Bit 5: MultiDropInt The MultiDropInt interrupt is set when the MAX3107 receives an address character in 9-bit multidrop mode (MODE2[6] is 1). This bit is cleared when SpclCharInt is read.
MAX3107 SPI/I2C UART with 128-Word FIFOs STSIntEn—STS Interrupt Enable Register ADDRESS: MODE: 0x07 R/W BIT 7 6 5 4 3 2 1 0 NAME — SleepIntEn ClkRdyIntEn — GPI3IntEn GPI2IntEn GPI1IntEn GPI0IntEn RESET 0 0 0 0 0 0 0 0 Bits 7 and 4: No Function Bit 6: SleepIntEn Set the SleepIntEn bit high to route the SleepInt status bit to the ISR[2]: STSInt. If set low, the STSIntEn masks the ISR[2] bit from SleepInt.
MAX3107 SPI/I2C UART with 128-Word FIFOs MODE1 Register ADDRESS: MODE: 0x09 R/W BIT 7 6 5 4 3 2 1 0 NAME IRQSel AutoSleep ForcedSleep TrnscvCtrl RTSHiZ TxHiZ TxDisabl RxDisabl RESET 0 0 0 0 0 0 0 0 Bit 7: IRQSel Depending on the logic level of the IRQSel bit, IRQ has different meanings. After a hardware or software (MODE2[0]) reset, the IRQSel bit is set low and after a short delay, the IRQ output signals the end of the MAX3107’s power-up sequence.
MAX3107 SPI/I2C UART with 128-Word FIFOs MODE2 Register ADDRESS: MODE: 0x0A R/W BIT 7 6 5 4 3 2 1 0 NAME EchoSuprs MultiDrop Loopback SpecialChr RxEmtyInv RxTrigInv FIFORst RST RESET 0 0 0 0 0 0 0 0 Bit 7: EchoSuprs Set the EchoSuprs bit high so that the MAX3107’s receiver gates any data it receives when its transmitter is busy transmitting. In half-duplex communication (like IrDA and RS-485) this allows blocking of the locally echoed data.
MAX3107 SPI/I2C UART with 128-Word FIFOs LCR—Line Control Register ADDRESS: MODE: 0x0B R/W BIT 7 6 5 4 3 2 1 0 NAME RTS TxBreak ForceParity EvenParity ParityEn StopBits Length1 Length0 RESET 0 0 0 0 0 1 0 1 Bit 7: RTS The RTS bit gives direct control of the RTS/CLKOUT output logic. If the RTS bit is set high, then RTS/CLKOUT is set to logic-high. The RTS bit only works if the CLKSource[7]:CLKtoRTS is not set high.
MAX3107 SPI/I2C UART with 128-Word FIFOs RxTimeOut—Receiver Timeout Register ADDRESS: MODE: 0x0C R/W BIT 7 6 5 4 3 2 1 0 NAME TimOut7 TimOut6 TimOut5 TimOut4 TimOutO3 TimOut2 TimOut1 TimOut0 RESET 0 0 0 0 0 0 0 0 Bits 7–0: TimOut[7:0] The receive data timeout bits allow programming a time delay after the last (newest) character in the receive FIFO was received until a receive data timeout LSR[0] interrupt is generated.
MAX3107 SPI/I2C UART with 128-Word FIFOs IrDA Register ADDRESS: MODE: 0x0E R/W BIT 7 6 5 4 3 2 1 0 NAME — — TxInv RxInv MIR — SIR IrDAEn RESET 0 0 0 0 0 0 0 0 The IrDA allows selection of IrDA SIR and MIR-compliant pulse shaping at the TX and RX interfaces. It also allows inversion of the TX and RX logic, independently of whether IrDA is enabled or not. Bits 7 and 6: No Function Bit 5: TxInv Set the TxInv bit high to invert the logic at the TX output.
MAX3107 SPI/I2C UART with 128-Word FIFOs FIFOTrgLvl—FIFO Interrupt Trigger Level Register ADDRESS: MODE: 0x10 R/W BIT 7 6 5 4 3 2 1 0 NAME RxTrig3 RxTrig2 RxTrig1 RxTrig0 TxTrig3 TxTrig2 TxTrig1 TxTrig0 RESET 1 1 1 1 1 1 1 1 Bits 7–4: RxTrig[3:0] These 4 bits allow definition of the receive FIFO threshold level at which an ISR[3] interrupt is generated.
MAX3107 SPI/I2C UART with 128-Word FIFOs FlowCtrl—Flow Control Register ADDRESS: MODE: 0x13 R/W BIT 7 6 5 4 3 2 1 0 NAME SwFlow3 SwFlow2 SwFlow1 SwFlow0 SwFlowEn GPIAddr AutoCTS AutoRTS RESET 0 0 0 0 0 0 0 0 Bits 7–4: SwFlow[3:0] The SwFlow[3:0] bits configure auto software flow control and/or special character detection in combination with the characters defined in the XON1, XON2, XOFF1 and/or XOFF2 registers. See Table 3.
MAX3107 SPI/I2C UART with 128-Word FIFOs Table 3. SwFlow[3:0] Truth Table SwFlow3 SwFlow2 SwFlow1 SwFlow0 TRANSMITTER FLOW CONTROL/SPECIAL CHARACTER DETECTION RECEIVER FLOW CONTROL DESCRIPTION 0 0 0 0 No flow control/no character detection. 0 0 X X No receiver flow control. 1 0 X X Transmitter generates XON1, XOFF1. 0 1 X X Transmitter generates XON2, XOFF2. 1 1 X X Transmitter generates XON1, XON2, XOFF1, and XOFF2. X X 0 0 No transmitter flow control.
MAX3107 SPI/I2C UART with 128-Word FIFOs XON2 Register ADDRESS: MODE: 0x15 R/W BIT 7 6 5 4 3 2 1 0 NAME Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 RESET 0 0 0 0 0 0 0 0 The XON1 and XON2 register contents define the XON characters for auto XON/XOFF flow control and/or the special characters used in special character detection. See details in the FlowCtrl register description.
MAX3107 SPI/I2C UART with 128-Word FIFOs XOFF2 Register ADDRESS: MODE: 0x17 R/W BIT 7 6 5 4 3 2 1 0 NAME Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 RESET 0 0 0 0 0 0 0 0 The XOFF1 and XOFF2 register contents define the XOFF characters for auto XON/XOFF flow control and/or special characters used in special character detection. See details in the FlowCtrl register description.
MAX3107 SPI/I2C UART with 128-Word FIFOs PLLConfig—PLL Configuration Register ADDRESS: MODE: 0x1A R/W BIT 7 6 5 4 3 2 1 0 NAME PLLFactor1 PLLFactor0 PreDiv5 PreDiv4 PreDiv3 PreDiv2 PreDiv1 PreDiv0 RESET 0 0 0 0 0 0 0 1 Bits 7 and 6: PLLFactor[1:0] The two PLLFactor[1:0] bits allow programming the PLL’s multiplication factor. The input and output frequencies of the PLL have to be limited to the ranges shown in Table 4. Enable the PLL through CLKSource[2].
MAX3107 SPI/I2C UART with 128-Word FIFOs BRGConfig—Baud-Rate Generator Configuration Register ADDRESS: MODE: 0x1B R/W BIT 7 6 5 4 3 2 1 0 NAME — — 4xMode 2xMode FRACT3 FRACT2 FRACT1 FRACT0 RESET 0 0 0 0 0 0 0 0 Bits 7 and 6: No Function Bit 5: 4xMode When the 4xMode bit is set high, the MAX3107 baud rate is quadruple the regular (16x sampling) baud rate. The 2xMode bit should be set low if 4xMode is enabled. See the 2x and 4x Rate Modes section for more information.
MAX3107 SPI/I2C UART with 128-Word FIFOs CLKSource—Clock Source Register ADDRESS: MODE: 0x1E R/W BIT 7 6 5 4 3 2 1 0 NAME CLKtoRTS — — ClockEn PLLBypass PLLEn CrystalEn — RESET 0 0 0 0 1 0 0 0 Bit 7: CLKtoRTS Set the CLKtoRTS bit to 1 to route the baud-rate generator (16x baud rate) output clock to RTS/CLKOUT. The clock frequency is a factor of 16x, 8x, or 4x of the baud rate, depending on the BRGConfig[5:4] settings.
MAX3107 SPI/I2C UART with 128-Word FIFOs Serial Controller Interface The MAX3107 can be controlled through SPI or I2C as defined by the logic on I2C/SPI. See the Pin Configurations for further details. SPI Interface the register address after each SPI data byte. Efficient programming of multiple consecutive registers is thus possible. Chip select, CS/A0, must be kept low during the whole cycle. The SCLK/SCL clock continues clocking throughout the burst access cycle.
MAX3107 SPI/I2C UART with 128-Word FIFOs S Sr P SCL SDA Figure 17. I2C START, STOP, and Repeated START Conditions Table 5. I2C Address Map DIN/A1 CS/A0 0 0 0 1 1 1 0 1 mode. The address is the first byte of information sent to the MAX3107 after the START condition.
MAX3107 SPI/I2C UART with 128-Word FIFOs WRITE SINGLE BYTE S DEVICE SLAVE ADDRESS - W A 8 DATA BITS A FROM MASTER TO STAVE REGISTER ADDRESS A P FROM SLAVE TO MASTER Figure 18. Write Byte Sequence BURST WRITE S DEVICE SLAVE ADDRESS - W A REGISTER ADDRESS A 8 DATA BITS - 1 A 8 DATA BITS - 2 A 8 DATA BITS - N A FROM MASTER TO STAVE P FROM SLAVE TO MASTER Figure 19.
MAX3107 SPI/I2C UART with 128-Word FIFOs BURST READ S DEVICE SLAVE ADDRESS - W A REGISTER ADDRESS A Sr DEVICE SLAVE ADDRESS - R A 8 DATA BITS - 1 A 8 DATA BITS - 2 A 8 DATA BITS - 3 A 8 DATA BITS - N A FROM MASTER TO STAVE P FROM SLAVE TO MASTER Figure 21. Burst Read Sequence 9) The slave sends 8 bits of data. S SCL 1 2 8 9 NOT ACKNOWLEDGE SDA ACKNOWLEDGE Figure 22. Acknowledge 8) T he addressed slave asserts an ACK on the data line. 9) The slave sends 8 data bits.
MAX3107 SPI/I2C UART with 128-Word FIFOs ENABLE INTERRUPTS POWER-UP/ RST INPUT PULLED HIGH/ RST BIT SET LOW CONFIGURE FIFO CONTROL IS IRQ HIGH? OR RevID READ SUCCESSFULLY N CONFIGURE FLOW CONTROL Y CONFIGURE CLOCKING CONFIGURE GPIOs CONFIGURE MODES START COMMUNICATION Figure 23. Startup and Initialization Flowchart To reduce the power consumption during normal operation, the following techniques can be adopted: • D o not use the internal PLL. This saves the most power of the options listed here.
MAX3107 SPI/I2C UART with 128-Word FIFOs 1.8V 3.3V 2.5V VL VDD VA VEXT RST MICROCONTROLLER TX DI RX RO RTS/CLKOUT DE MAX3107 SPI/I2C IRQ AGND VCC MAX3078 TRANSCEIVER DGND Figure 24. Logic-Level Translation RS-232 5x3 Application TX MAX3107 RX SHARED CONNECTOR TX/D+ RX/D- D+ OE MAX13481E D- Figure 25. Connector Sharing with a USB Transceiver Connector Pin Sharing The TX and RTS/CLKOUT outputs can be programmed to be high impedance.
MAX3107 SPI/I2C UART with 128-Word FIFOs MAX3245 SPI/I2C MAX3107 TX T1IN RX R1OUT RTS/CLKOUT RST CTS MICROCONTROLLER IRQ Tx Rx T2IN RTS R2OUT GPIO0 T3IN GPIO1 R3OUT GPIO2 R4OUT GPIO3 R5OUT CTS DTR DSR LDOEN DCD RI Figure 26. RS-232 Application 3.3V 100nF VEXT VA VL TX LDOEN SPI/I2C RTS 10kΩ IRQ MICROCONTROLLER MAX3107 RX DI A DE B RO RE SPI MAX14840 RST CLOCK XIN AGND XOUT V18 DGND 1µF 100nF Figure 27.
MAX3107 SPI/I2C UART with 128-Word FIFOs Functional Diagram VA V18 VL LDOEN VEXT LDO I2C/SPI TX AND FIFO DIN/A1 TX SPI/I2C DOUT/SDA CS/A0 SCLK/SCL REGISTERS AND CONTROL LOGIC-LEVEL TRANSLATION CTS FLOW CONTROL RTS/CLKOUT LOGIC-LEVEL TRANSLATION RST RX Rx AND FIFO IRQ GPIO0 XIN CRYSTAL OSCILLATOR XOUT DIVIDER FRACTIONAL BAUD-RATE GENERATOR PLL GPIO1 GPIO GPIO2 GPIO3 MAX3107 AGND DGND Package Information For the latest package outline information and land patterns (footprints),
MAX3107 SPI/I2C UART with 128-Word FIFOs Revision History REVISION NUMBER REVISION DATE 0 10/09 Initial release — 4/10 Changed the maximum number for the “External Clock Frequency” specification from 30MHz to 35MHz in the AC Electrical Characteristics table 8 Replaced the text in the SPI Burst Access section 44 4/10 Increased the maximum VIL specification for the XIN Clock Input in the Electrical Characteristics from 0.2V to 0.