MAX3109 Dual Serial UART with 128-Word FIFOs General Description The MAX3109 advanced dual universal asynchronous receiver-transmitter (UART) has 128 words of receive and transmit first-in/first-out (FIFO) and a high-speed SPI or I2C controller interface. The 2x and 4x rate modes allow a maximum of 24Mbps data rates. A phase-locked loop (PLL) and the fractional baud-rate generators allow a high degree of flexibility in baud-rate programming and reference clock selection.
MAX3109 Dual Serial UART with 128-Word FIFOs TABLE OF CONTENTS Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Package Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MAX3109 Dual Serial UART with 128-Word FIFOs TABLE OF CONTENTS (continued) FIFO Interrupt Triggering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Low-Power Standby Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Forced-Sleep Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MAX3109 Dual Serial UART with 128-Word FIFOs LIST OF FIGURES Figure 1. I2C Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Figure 2. SPI Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Figure 3. Transmit FIFO Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MAX3109 Dual Serial UART with 128-Word FIFOs LIST OF TABLES Table 1. StopBits Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Table 2. Lengthx Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Table 3. SwFlow[3:0] Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MAX3109 Dual Serial UART with 128-Word FIFOs LIST OF REGISTERS (continued) GPIO Data Register (GPIOData) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 PLL Configuration Register (PLLConfig) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Baud-Rate Generator Configuration Register (BRGConfig) . . . . . . . . . . . . . . . . . . . . . . . . . . .
MAX3109 Dual Serial UART with 128-Word FIFOs ABSOLUTE MAXIMUM RATINGS (Voltages referenced to AGND.) VL, VCC, VEXT, XIN................................................-0.3V to +4.0V XOUT......................................................... -0.3V to (VCC + 0.3V) V18....................... -0.3V to the lesser of (VCC + 0.3V) and 2.0V RST, IRQ, MOSI/A1, CS/A0, SCLK/SCL, MISO/SDA, LDOEN, SPI/I2C..................... -0.3V to (VL + 0.3V) TX_, RX_, CTS_, GPIO_............................ -0.3V to (VEXT + 0.
MAX3109 Dual Serial UART with 128-Word FIFOs DC ELECTRICAL CHARACTERISTICS (continued) (VCC = 1.71V to 3.6V, VL = 1.71V to 3.6V, VEXT = 1.71V to 3.6V, TA = -40NC to +85NC, unless otherwise noted. Typical values are at VCC = 2.8V, VL = 1.8V, VEXT = 2.5V, TA = +25NC.
MAX3109 Dual Serial UART with 128-Word FIFOs DC ELECTRICAL CHARACTERISTICS (continued) (VCC = 1.71V to 3.6V, VL = 1.71V to 3.6V, VEXT = 1.71V to 3.6V, TA = -40NC to +85NC, unless otherwise noted. Typical values are at VCC = 2.8V, VL = 1.8V, VEXT = 2.5V, TA = +25NC.) (Notes 2, 3) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 0.
MAX3109 Dual Serial UART with 128-Word FIFOs AC ELECTRICAL CHARACTERISTICS (VCC = 1.71V to 3.6V, VL = 1.71V to 3.6V, VEXT = 1.71V to 3.6V TA = -40NC to +85NC, unless otherwise noted. Typical values are at VCC = 2.8V, VL = 1.8V, VEXT = 2.5V, TA = +25NC.) (Notes 2, 3) PARAMETER SYMBOL External Cystal Frequency fXOSC External Clock Frequency fCLK External Clock Duty Cycle Baud-Rate Generator Clock Input Frequency CONDITIONS MAX UNITS 4 MHz 0.
MAX3109 Dual Serial UART with 128-Word FIFOs AC ELECTRICAL CHARACTERISTICS (continued) (VCC = 1.71V to 3.6V, VL = 1.71V to 3.6V, VEXT = 1.71V to 3.6V TA = -40NC to +85NC, unless otherwise noted. Typical values are at VCC = 2.8V, VL = 1.8V, VEXT = 2.5V, TA = +25NC.) (Notes 2, 3) PARAMETER SYMBOL CONDITIONS Standard mode Setup Time for STOP Condition tSU:STO Capacitive Load for SDA and SCL CB SCL and SDA I/O Capacitance CI/O Pulse Width of Spike Suppressed tSP MIN TYP MAX UNITS 4.
MAX3109 Dual Serial UART with 128-Word FIFOs Timing Diagrams START CONDITION (S) REPEATED START CONDITION (Sr) tR STOP CONDITION (P) tF SDA tBUF tHD:DAT tHD:STA tHD:STA tSU:DAT tSU:STO tSU:STA SCL tHIGH tR tF START CONDITION (S) tLOW Figure 1. I2C Timing Diagram CS tCSS tCSH tCL tCH tCSH SCLK tDS tDH MOSI tDO MISO tFT Figure 2.
MAX3109 Dual Serial UART with 128-Word FIFOs Typical Operating Characteristics (VCC = 2.5V, VL = 2.5V, VEXT = 2.5V, VLDOEN = VL, UART1 in sleep mode, TA = +25°C unless otherwise noted.) SOURCE CURRENT (PUSH-PULL) vs. GPIO_OUTPUT HIGH VOLTAGE SINK CURRENT (OPEN DRAIN) vs. GPIO_ OUTPUT LOW VOLTAGE 140 60 50 ISOURCE (mA) VEXT = 3.6V 120 100 80 VEXT = 2.5V 60 MAX3109 toc02 160 ISINK (mA) 70 MAX3109 toc01 180 VEXT = 2.5V VEXT = 3.3V 40 30 VEXT = 1.8V 20 40 10 20 VEXT = 1.
MAX3109 Dual Serial UART with 128-Word FIFOs GPIO2 RTS1 RTS0 RX1 RX0 TX0 TX1 TOP VIEW GPIO3 Pin Configuration 24 23 22 21 20 19 18 17 16 CTS1 XIN 26 15 CTS0 XOUT 27 14 GPIO5 13 GPIO1 AGND 29 12 GPIO4 LDOEN 30 11 GPIO0 10 DGND 9 SPI/I2C VEXT 25 GPIO6 28 MAX3109 V18 31 *EP + 4 5 6 7 8 CS/A0 MOSI/A1 IRQ VL MISO/SDA 3 GPIO7 2 SCLK/SCL 1 RST VCC 32 TQFN (5mm × 5mm) *CONNECT EP TO AGND. Pin Description PIN NAME 1 RST 2 MISO/SDA Serial-Data Output.
MAX3109 Dual Serial UART with 128-Word FIFOs Pin Description (continued) PIN NAME FUNCTION 8 VL Digital Interface Power Supply. VL powers the internal logic-level translators for RST, IRQ, MOSI/A1, CS/A0, SCLK/SCL, MISO/SDA, LDOEN, and SPI/I2C. Bypass VL with a 0.1FF ceramic capacitor to DGND. 9 SPI/I2C SPI Selector Input or Active-Low I2C. Drive SPI/I2C low to enable I2C. Drive SPI/I2C high to enable SPI. 10 DGND Digital Ground GPIO0 General-Purpose Input/Output 0.
MAX3109 Dual Serial UART with 128-Word FIFOs Pin Description (continued) PIN NAME FUNCTION 27 XOUT Crystal Output. When using an external crystal, connect one end of the crystal to XOUT and the other end to XIN. When using an external clock source, leave XOUT unconnected. 28 GPIO6 General-Purpose Input/Output 6. GPIO6 is user-programmable as input or output (push-pull or open drain) or an external event-driven interrupt source. GPIO6 has a weak pulldown resistor to DGND when configured as an input.
MAX3109 Dual Serial UART with 128-Word FIFOs The contents of the TxFIFO and RxFIFO are both cleared when the MODE2[1]: FIFORst bit is set high .Transmitter Operation Figure 3 shows the structure of the transmitter with the TxFIFO. The transmit FIFO can hold up to 128 words of data that are added by writing to the THR register. The current number of words in the TxFIFO can be read out by the host controller through the TxFIFOLvl register.
MAX3109 Dual Serial UART with 128-Word FIFOs RECEIVED DATA RX_ RECEIVER LSR[1] ISR[3] OVERRUN WORD TRIGGER The following three error conditions are checked for each received word: parity error, frame error, and noise on the line. Parity errors are detected by calculating either even or odd parity of the received word as programmed by register settings. Framing errors are detected when the received data frame does not match the expected frame format in length.
MAX3109 Dual Serial UART with 128-Word FIFOs CrystalEn XOUT XIN PLLBypass FRACTIONAL BAUD-RATE GENERATOR 0 CRYSTAL OSCILLATOR DIVIDER PLL FRACTIONAL BAUD-RATE GENERATOR 1 PLLEn Figure 7. Clock Selection Diagram Clock Selection The MAX3109 can be clocked by either an external crystal or an external clock source. Figure 7 shows a simplified diagram of the clock selection circuitry.
MAX3109 Dual Serial UART with 128-Word FIFOs The following is an example of how to calculate the divisor. It is based on a required baud rate of 190kbaud and a reference input frequency of 28.23MHz and 1x (default) rate mode. The ideal divisor is calculated as: D = 28,230,000/(16 x 190,000) = 9.286 hence DIV = 9. FRACT = ROUND(16 x 0.286) = 5 so DIVMSB = 0x00, DIVLSB = 0x09, and BRGConfig[3:0] = 0x05. the usual three samples to determine the logic value of the received bit.
MAX3109 Dual Serial UART with 128-Word FIFOs UART Clock to GPIO The MAX3109 reference clock can be routed to the GPIO0 and/or GPIO4 outputs if a synchronous highfrequency clock is needed by another device. Enable routing a UART clock to GPIO0 and/or GPIO4 in the TxSynch register. This output clock could, for example, be used to clock another UART device.
MAX3109 Dual Serial UART with 128-Word FIFOs TRANSMITTER DI TX_ D TxFIFO DE MAX3109 AUTO TRANSCEIVER CONTROL RxFIFO RECEIVER B RTS_ RE RX_ RO MAX14840E A R Figure 10. Auto Transceiver Direction Control RTS_ SETUP HOLD TX_ FIRST CHARACTER LAST CHARACTER Figure 11. Setup and Hold Times in Auto Transceiver Direction Control Enable and configure transmitter synchronization with the TxSynch register.
MAX3109 Dual Serial UART with 128-Word FIFOs Both portions of the delay are dependent on the UART’s clock. When the fractional divider is not used, the intrinsic trigger delay, tTRIG, is bounded by the following limits: 5 6 ≤ t TRIG ≤ UARTCLK UARTCLK where UARTCLK is the baud-rate divider output. The reference point is the time when the trigger command is received by the MAX3109. This occurs on the final (i.e., the 16th) SPI clock’s low-to-high transition (Figure 12).
MAX3109 Dual Serial UART with 128-Word FIFOs trigger accuracy equation for a single transmitter output. Calculate the TX_ transmitter output skew using the following equation: 6 5 t TRIGSKEW ≤ − (UARTCLK) S (UARTCLK) F where (UARTCLK)S is the fractional divider output clock of the lower/slower baud rate UART, and (UARTCLK)F is the fractional divider output clock of the higher/faster baud rate UART. Auto Transmitter Disable The MAX3109 allows automatic disabling of the transmitter.
MAX3109 Dual Serial UART with 128-Word FIFOs STOP BIT TX_ HOLD DELAY DI TO RO PROPAGATION DELAY RX_ RTS_ Figure 15. Echo Suppression Timing levels in the FlowLvl register. With differing HALT and RESUME levels, hysteresis of the RxFIFO level can be defined for RTS_ transitions. When the RxFIFO is filled to a level higher than the HALT level, the MAX3109 deasserts RTS_ and stops the farend UART from transmitting any additional data.
MAX3109 Dual Serial UART with 128-Word FIFOs at which the XOFF and XON characters are sent. HALT and RESUME are programmed in the FlowLvl register. With differing HALT and RESUME levels, hysteresis can be defined in the RxFIFO fill level for the receiver flow control activity. When the RxFIFO is filled to a level higher than the HALT level, the MAX3109 sends an XOFF character to stop data transmission.
MAX3109 Dual Serial UART with 128-Word FIFOs Shutdown Mode Drive the RST input to logic-low to enter shutdown mode. Shutdown mode consumes less than 1FA. In shutdown mode, all the MAX3109 circuitry is completely off. This includes the I2C/SPI interface, the registers, the FIFOs, and the clocking circuitry. Interrupt Structure Figure 16 shows the structure of the interrupt. There are four interrupt source registers: ISR, LSR, STSInt, and SpclCharInt.
MAX3109 Dual Serial UART with 128-Word FIFOs Register Map (Note: All default reset values are 0x00, unless otherwise noted. All registers are R/W, unless otherwise noted.
MAX3109 Dual Serial UART with 128-Word FIFOs Detailed Register Descriptions The MAX3109 has 8-bit-wide registers. When using SPI control, the extended register location (0x20 through 0x25) can only be accessed by first enabling extended read/writing through GloblComnd. Each UART has an exclusive set of registers. Select a UART to write to by setting the U bit of the command byte in SPI mode or the unique I2C address in I2C mode (see the Serial Controller Interface section for more information).
MAX3109 Dual Serial UART with 128-Word FIFOs IRQ Enable Register (IRQEn) ADDRESS: MODE: 0x01 R/W BIT 7 6 5 4 3 2 1 0 NAME CTSIEn RxEmtyIEn TFifoEmtyIEn TxTrgIEn RxTrgIEn STSIEn SpChrIEn LSRErrIEn RESET 0 0 0 0 0 0 0 0 The IRQEn register is used to enable the IRQ physical interrupt. Any of the eight ISR interrupt sources can be enabled to generate an interrupt on IRQ. The IRQEn bits only influence the IRQ output and do not have any effect on the ISR contents or behavior.
MAX3109 Dual Serial UART with 128-Word FIFOs Interrupt Status Register (ISR) ADDRESS: MODE: 0x02 COR BIT 7 6 5 4 3 2 1 0 NAME CTSInt RxEmptyInt TFifoEmptyInt TxTrigInt RxTrigInt STSInt SpCharInt LSRErrInt RESET 0 1 1 0 0 0 0 0 The Interrupt Status register provides an overview of all interrupts generated by the MAX3109. Both the interrupt bits and any pending interrupts on IRQ are cleared after reading ISR.
MAX3109 Dual Serial UART with 128-Word FIFOs Line Status Interrupt Enable Register (LSRIntEn) ADDRESS: MODE: 0x03 R/W BIT 7 6 5 4 3 2 1 0 NAME — — NoiseIntEn RBreakIEn FrameErrIEn ParityIEn ROverrIEn RTimoutIEn RESET 0 0 0 0 0 0 0 0 LSRIntEn allows routing of LSR interrupts to ISR[0]. The LSRIntEn bits only influence the ISR[0]: LSRErrInt bit and do not have any effect on the LSR contents or behavior.
MAX3109 Dual Serial UART with 128-Word FIFOs Line Status Register (LSR) ADDRESS: MODE: 0x04 R BIT NAME RESET 7 6 5 4 3 2 1 0 CTSbit X — RxNoise RxBreak FrameErr RxParityErr RxOverrun RTimeout 0 0 0 0 0 0 0 LSR contains all error information related to the word most recently read out from the RxFIFO through RHR.
MAX3109 Dual Serial UART with 128-Word FIFOs The timeout counter restarts whenever RHR is read or a new character is received by the RxFIFO. If the value in RxTimeOut is zero, RTimeout is disabled. RTimeout is cleared after a word is read out of the RxFIFO or a new word is received. RTimeout generates an interrupt in ISR[0] if enabled by LSRIntEn[0].
MAX3109 Dual Serial UART with 128-Word FIFOs Special Character Interrupt Register (SpclCharInt) ADDRESS: MODE: 0x06 COR BIT 7 6 5 4 3 2 1 0 NAME — — MultiDropInt BREAKInt XOFF2Int XOFF1Int XON2Int XON1Int RESET 0 0 0 0 0 0 0 0 SpclCharInt contains interrupts that are generated when a special character is received, an address is received in multidrop mode, or a line break occurs.
MAX3109 Dual Serial UART with 128-Word FIFOs STS Interrupt Enable Register (STSIntEn) ADDRESS: MODE: 0x07 R/W BIT 7 6 5 4 3 2 1 0 NAME TxEmptyIntEn SleepIntEn ClkRdyIntEn — GPI3IntEn GPI2IntEn GPI1IntEn GPI0IntEn RESET 0 0 0 0 0 0 0 0 STSIntEn allows routing of STSInt interrupts to ISR[2].
MAX3109 Dual Serial UART with 128-Word FIFOs Status Interrupt Register (STSInt) ADDRESS: MODE: 0x08 R/COR BIT 7 6 5 4 3 2 1 0 NAME TxEmptyInt SleepInt ClkReady — GPI3Int GPI2Int GPI1Int GPI0Int RESET 0 0 0 0 0 0 0 0 Bit 7: TxEmptyInt The TxEmptyInt interrupt is generated when both the TxFIFO is empty and the last character has completed transmission. TxEmptyInt is cleared after STSInt is read. TxEmptyInt generates an interrupt in ISR[2] if enabled by STSIntEn[7].
MAX3109 Dual Serial UART with 128-Word FIFOs MODE1 Register ADDRESS: MODE: 0x09 R/W BIT 7 6 5 4 3 2 1 0 NAME — AutoSleep ForcedSleep TrnscvCtrl RTSHiZ TxHiZ TxDisabl RxDisabl RESET 0 0 0 0 0 0 0 0 Bit 6: AutoSleep Set the AutoSleep bit high to set the MAX3109 to automatically enter low-power sleep mode after a period of no activity (see the Auto-Sleep Mode section). An interrupt is generated in STSInt[6]: SleepInt when the MAX3109 enters sleep mode.
MAX3109 Dual Serial UART with 128-Word FIFOs MODE2 Register ADDRESS: MODE: 0x0A R/W BIT 7 6 5 4 3 2 1 0 NAME EchoSuprs MultiDrop Loopback SpecialChr RFifoEmptyInv RxTrigInv FIFORst RST RESET 0 0 0 0 0 0 0 0 Bit 7: EchoSuprs Set the EchoSuprs bit high to discard any data that the MAX3109 receives when its transmitter is busy transmitting. In half-duplex communication such as RS-485 and IrDA, this allows blocking of the locally echoed data.
MAX3109 Dual Serial UART with 128-Word FIFOs Line Control Register (LCR) ADDRESS: MODE: 0x0B R/W BIT 7 6 5 4 3 2 1 0 NAME RTSbit 0 TxBreak ForceParity EvenParity ParityEn StopBits Length1 Length0 0 0 0 0 1 0 1 RESET Bit 7: RTSbit The RTSbit bit provides direct control of the RTS_ output logic state. If RTSbit is logic 1, then RTS_ is logic 1; if it is logic 0, then RTS_ is logic 0. RTSbit only works when CLKSource[7]: CLKtoRTS is set low.
MAX3109 Dual Serial UART with 128-Word FIFOs Receiver Timeout Register (RxTimeOut) ADDRESS: MODE: 0x0C R/W BIT 7 6 5 4 3 2 1 0 NAME TimOut7 TimOut6 TimOut5 TimOut4 TimOut3 TimOut2 TimOut1 TimOut0 RESET 0 0 0 0 0 0 0 0 Bits 7–0: TimOutx The RxTimeOut register allows programming a time delay from after the last (newest) character in the receive FIFO was received until a receive data timeout interrupt is generated in LSR[0].
MAX3109 Dual Serial UART with 128-Word FIFOs IrDA Register ADDRESS: MODE: 0x0E R/W BIT 7 6 5 4 3 2 1 0 NAME — — TxInv RxInv MIR — SIR IrDAEn RESET 0 0 0 0 0 0 0 0 The IrDA register allows selection of IrDA SIR- and MIR-compliant pulse shaping at the TX_ and RX_ interfaces. It also allows inversion of the TX_ and RX_ logic, separate from whether IrDA pulse shaping is enabled or not.
MAX3109 Dual Serial UART with 128-Word FIFOs FIFO Interrupt Trigger Level Register (FIFOTrgLvl) ADDRESS: MODE: 0x10 R/W BIT 7 6 5 4 3 2 1 0 NAME RxTrig3 RxTrig2 RxTrig1 RxTrig0 TxTrig3 TxTrig2 TxTrig1 TxTrig0 RESET 1 1 1 1 1 1 1 1 Bits 7–4: RxTrigx The RxTrigx bits allow definition of the receive FIFO threshold level at which the UART generates an interrupt in ISR[3].
MAX3109 Dual Serial UART with 128-Word FIFOs Flow Control Register (FlowCtrl) ADDRESS: MODE: 0x13 R/W BIT 7 6 5 4 3 2 1 0 NAME SwFlow3 SwFlow2 SwFlow1 SwFlow0 SwFlowEn GPIAddr AutoCTS AutoRTS RESET 0 0 0 0 0 0 0 0 The FlowCtrl register configures hardware (RTS/CTS) and software (XON/XOFF) flow control as well as special characters detection.
MAX3109 Dual Serial UART with 128-Word FIFOs Table 3. SwFlow[3:0] Truth Table RECEIVE FLOW CONTROL TRANSMIT FLOW CONTROL/SPECIAL CHARACTER DETECTION DESCRIPTION SwFlow3 SwFlow2 SwFlow1 SwFlow0 0 0 0 0 No flow control/no special character detection. 0 0 X X No receive flow control. 1 0 X X Transmitter generates XON1, XOFF1. 0 1 X X Transmitter generates XON2, XOFF2. 1 1 X X Transmitter generates XON1, XON2, XOFF1, and XOFF2. X X 0 0 No transmit flow control.
MAX3109 Dual Serial UART with 128-Word FIFOs XON2 Register ADDRESS: MODE: 0x15 R/W BIT 7 6 5 4 3 2 1 0 NAME Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 RESET 0 0 0 0 0 0 0 0 The XON1 and XON2 register contents define the XON character for automatic XON/XOFF flow control and/or the special characters used in special-character detection. See the FlowCtrl register description for more information.
MAX3109 Dual Serial UART with 128-Word FIFOs XOFF2 Register ADDRESS: MODE: 0x17 R/W BIT 7 6 5 4 3 2 1 0 NAME Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 RESET 0 0 0 0 0 0 0 0 The XOFF1 and XOFF2 register contents define the XOFF character for automatic XON/XOFF flow control and/or the special characters used in special character detection. See the FlowCtrl register description for more information.
MAX3109 Dual Serial UART with 128-Word FIFOs GPIO Data Register (GPIOData) ADDRESS: MODE: 0x19 R/W BIT 7 6 5 4 3 2 1 0 NAME GPI3Dat GPI2Dat GPI1Dat GPI0Dat GPO3Dat GPO2Dat GPO1Dat GPO0Dat RESET 0 0 0 0 0 0 0 0 Each UART has four individually assigned GPIO outputs as follows: UART0: GPIO0–GPIO3, UART1: GPIO4–GPIO7. Bits 7–4: GPIxDat The GPIxDat bits reflect the input logic on the associated GPIO_s.
MAX3109 Dual Serial UART with 128-Word FIFOs PLL Configuration Register (PLLConfig) ADDRESS: MODE: 0x1A R/W BIT 7 6 5 4 3 2 1 0 NAME PLLFactor1 PLLFactor0 PreDiv5 PreDiv4 PreDiv3 PreDiv2 PreDiv1 PreDiv0 RESET 0 0 0 0 0 0 0 1 Bits 7–6: PLLFactorx The PLLFactorx bits allow programming the PLL multiplication factor. The input and output frequencies of the PLL must be limited to the ranges shown in Table 4. Enable the PLL in CLKSource[2].
MAX3109 Dual Serial UART with 128-Word FIFOs Baud-Rate Generator Configuration Register (BRGConfig) ADDRESS: MODE: 0x1B R/W BIT 7 6 5 4 3 2 1 0 NAME — — 4xMode 2xMode FRACT3 FRACT2 FRACT1 FRACT0 RESET 0 0 0 0 0 0 0 0 Bits 7 and 6: No Function Bit 5: 4xMode Set the 4xMode bit high to quadruple the regular (16x sampling) baud rate. Set the 2xMode bit low when 4xMode is enabled. See the 2x and 4x Rate Modes section for more information.
MAX3109 Dual Serial UART with 128-Word FIFOs Baud-Rate Generator MSB Divisor Register (DIVMSB) ADDRESS: MODE: 0x1D R/W BIT 7 6 5 4 3 2 1 0 NAME Div15 Div14 Div13 Div12 Div11 Div10 Div9 Div8 RESET 0 0 0 0 0 0 0 0 DIVLSB and DIVMSB define the baud-rate generator integer divisor. The minimum value for DIVLSB is 1. See the Fractional Baud-Rate Generator section for more information.
MAX3109 Dual Serial UART with 128-Word FIFOs Global IRQ Register (GlobalIRQ) ADDRESS: MODE: 0x1F R BIT 7 6 5 4 3 2 1 0 NAME — — — — — — RESET 0 0 0 0 0 0 IRQ1 1 IRQ0 1 Bit 7–2: No Function Bits 1-0: IRQx The MAX3109 has a single IRQ output. The GlobalIRQ register bits report which of the UARTs have an interrupt pending, as enabled in the ISRIntEn registers.
MAX3109 Dual Serial UART with 128-Word FIFOs Global Command Register (GloblComnd) ADDRESS: MODE: 0x1F W BIT 7 6 5 4 3 2 1 0 NAME GlbCom7 GlbCom6 GlbCom5 GlbCom4 GlbCom3 GlbCom2 GlbCom1 GlbCom0 Bits 7–0: GlbComx The GloblComnd register is the only global write register in the MAX3109. Every byte written to GloblComnd is sent simultaneously to both UARTs.
MAX3109 Dual Serial UART with 128-Word FIFOs Transmitter Synchronization Register (TxSynch) ADDRESS: MODE: 0x20 R/W BIT 7 6 5 4 3 2 1 0 NAME CLKtoGPIO TxAutoDis TrigDelay SynchEn TrigSel3 TrigSel2 TrigSel1 TrigSel0 RESET 0 0 0 0 0 0 0 0 The TxSynch register is used to configure transmitter synchronization with a global SPI or I2C command. One of 16 trigger commands (Table 5) can be selected to be the synchronization trigger source individually for each UART.
MAX3109 Dual Serial UART with 128-Word FIFOs Synchronization Delay Register 1 (SynchDelay1) ADDRESS: MODE: 0x21 R/W BIT 7 6 5 4 3 2 1 0 NAME SDelay7 SDelay6 SDelay5 SDelay4 SDelay3 SDelay2 SDelay1 SDelay0 RESET 0 0 0 0 0 0 0 0 The SynchDelay1 and SynchDelay2 register contents define the time delay between when the UART receives an assigned transmitter trigger command and when the UART begins transmission.
MAX3109 Dual Serial UART with 128-Word FIFOs Timer Register 1 (TIMER1) ADDRESS: MODE: 0x23 R/W BIT 7 6 5 4 3 2 1 0 NAME Timer7 Timer6 Timer5 Timer4 Timer3 Timer2 Timer1 Timer0 RESET 0 0 0 0 0 0 0 0 The TIMER1 and TIMER2 register contents can be used to generate a low-frequency clock signal on a GPIO_ output. The low-frequency clock is a divided replica of the fractional baud-rate generator output. If TIMER1 and TIMER2 are both 0x00, the low-frequency clock is off.
MAX3109 Dual Serial UART with 128-Word FIFOs Serial Controller Interface To access the registers with addresses 0x20 or higher in SPI mode, enable extended register map access. See the GloblComnd register description for more information. The MAX3109 can be controlled through I2C or SPI as defined by the logic on SPI/I2C. See the Pin Description for further details. SPI Single-Cycle Access Before a specific UART has been addressed, both UARTs could attempt to drive MISO.
MAX3109 Dual Serial UART with 128-Word FIFOs CS SCLK R MOSI 0 U A4 A3 A2 0 0 A1 A0 IRQ1 IRQ0 HIGH-Z MISO Ax = REGISTER ADDRESS Figure 20. SPI Fast Read Cycle SPI Burst Access Burst access allows writing and reading multiple data bytes in one block by defining only the initial register address in the SPI command byte. Multiple characters can be loaded into the TxFIFO by using the THR (0x00) as the initial burst write address.
MAX3109 Dual Serial UART with 128-Word FIFOs bus, or a repeated START condition (Sr) to communicate to another I2C slave. See Figure 21. first byte of information sent to the MAX3109 after the START condition. Slave Address The MAX3109 includes a configurable 7-bit I2C slave address, allowing up to 16 MAX3109 devices to share the same I2C bus. The address is defined by connecting the MOSI/A1 and CS/A0 inputs to DGND, VL, SCL, or SDA (Table 5). Set the R/W bit high to configure the MAX3109 to read mode.
MAX3109 Dual Serial UART with 128-Word FIFOs WRITE SINGLE BYTE S DEVICE SLAVE ADDRESS - W A 8 DATA BITS A FROM MASTER TO STAVE REGISTER ADDRESS A P FROM SLAVE TO MASTER Figure 22. Write Byte Sequence BURST WRITE S DEVICE SLAVE ADDRESS - W A REGISTER ADDRESS A 8 DATA BITS - 1 A 8 DATA BITS - 2 A 8 DATA BITS - N A FROM MASTER TO STAVE P FROM SLAVE TO MASTER Figure 23.
MAX3109 Dual Serial UART with 128-Word FIFOs Single-Byte Read In this operation, the master sends an address plus two data bytes and receives one data byte from the slave device (Figure 24). The following procedure describes the single-byte read operation: 10) The master asserts a NACK on the data line. 11) The master generates a STOP condition. Burst Read In this operation, the master sends an address plus two data bytes and receives multiple data bytes from the slave device (Figure 25).
MAX3109 Dual Serial UART with 128-Word FIFOs 8) The slave asserts an ACK on the data line. 9) The slave sends 8 data bits. 10) The master asserts an ACK on the data line. 11) Repeat 9 and 10 N-2 times. 12) The slave sends the last 8 data bits. 13) The master asserts a NACK on the data line. 14) The master generates a STOP condition. Applications Information S SCL Acknowledge Bits Data transfers are acknowledged with an acknowledge bit (ACK) or a not-acknowledge bit (NACK).
MAX3109 Dual Serial UART with 128-Word FIFOs 1.8V 3.3V 2.5V VL VCC VDD VEXT RST MICROCONTROLLER MAX3109 SPI/I2C IRQ AGND VCC TX_ DI RX_ RO RTS_ DE MAX14840E TRANSCEIVER DGND Figure 28. Logic-Level Translation Low-Power Operation To reduce the power consumption during normal operation, the following techniques can be adopted: • Do not use the internal PLL. This saves the most power of the options listed here. Disable and bypass the PLL.
MAX3109 Dual Serial UART with 128-Word FIFOs Power-Supply Sequencing The device’s power supplies can be turned on in any order. Each supply can be present over the entire specified range regardless of the presence or level of the others. Ensure the presence of the interface supplies VL and VEXT before sending input signals to the controller and transceiver interfaces.
MAX3109 Dual Serial UART with 128-Word FIFOs 3.3V 0.1µF VCC LDOEN VEXT VL TX0 SPI/I2C RTS0 10kΩ MAX3109 IRQ RX0 DI A1 DE B1 RO RE SPI MAX14840E MICROCONTROLLER XIN XOUT TX1 RST RTS1 AGND RX1 DGND V18 DI A2 DE B2 RO RE 1µF MAX14840E Figure 31. RS-485 Half-Duplex Application Typical Application Circuit Figure 31 shows the MAX3109 being used in a halfduplex RS-485 application. The microcontroller, the RS-485 transceiver, and the MAX3109 are powered by a single 3.3V supply.
MAX3109 Dual Serial UART with 128-Word FIFOs Revision History REVISION NUMBER REVISION DATE 0 3/11 Initial release 1 5/12 Corrected for improved shutdown current mode and specifications, including lowpower shutdown mode configurations 1, 7, 14, 15, 27, 38, 62 2 10/12 Updated DC Electrical Characteristics, updated Pin Description, updated Register Map, updated recommended capacitor value, updated IRQ text, updated Figure 31 9, 16, 28, 52, 56, 65 DESCRIPTION PAGES CHANGED — Maxim cannot assume