Revision 0; 8/11 MAX31782 User’s Guide Functional Diagrams Pin Configurations appear at end of data sheet. Functional Diagrams continued at end of data sheet. UCSP is a trademark of Maxim Integrated Products, Inc.
MAX31782 User’s Guide TABLE OF CONTENTS SECTION 1: Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 SECTION 2: Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MAX31782 User’s Guide SECTION 1: OVERVIEW The MAX31782 system management microcontroller provides a complete solution for the monitoring and controlling of complex system physical health characteristics. The MAX31782 is based on the high-performance 16-bit family of MAXQM reduced instruction set computing (RISC) microcontrollers. The MAX31782 provides generous amounts of flash program memory and SRAM data memory.
MAX31782 User’s Guide Some of the resources and features that the MAX31782 provides for monitoring and controlling a complex system include the following: • Remote temperature measurement of diode connected transistors on up to 6 channels • Accurate voltage measurement using the 12-bit analog to digital converter (ADC) on up to 6 channels • Internal temperature sensor • Independent slave and master I2C-compatable interfaces • Six independent PWM outputs and tachometer Inputs • Hardware multiplier unit • 32K
MAX31782 User’s Guide SECTION 2: ARCHITECTURE This section contains the following information: 2.1 Instruction Decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 2.2 Register Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MAX31782 User’s Guide SECTION 2: ARCHITECTURE The MAX31782 contains a MAXQ20 low-cost, high-performance, CMOS, fully static microcontroller with flash memory. It is structured on a highly advanced, 16-accumulator-based, 16-bit RISC architecture. Fetch and execution operations are completed in one cycle without pipelining, since the instruction contains both the op code and data.
MAX31782 User’s Guide This instruction word format presents the following limitations. 1) There are 32 registers per register module, but only 4 bits are allocated to designate the source register and only 3 bits are allocated to designate the destination register. 2) The source field only provides 8 bits of data for an immediate value; however, a 16-bit immediate value can be required. The MAX31782 uses a prefix register (PFX) to address these limitations.
MAX31782 User’s Guide Registers can be 8 or 16 bits in length. Some registers can contain reserved bits. The user should not write to any reserved bits. Data transfers between registers of different sizes are handled as shown in Table 2-1. • If the source and destination registers are both 8 bits wide, data is copied bit to bit.
MAX31782 User’s Guide 2.3.2 SRAM Memory The MAX31782 contains 1KWords (1K x 16) of SRAM memory. The SRAM memory address begins at address 0000h and is contiguous through word address 03FFh. The contents of the SRAM are indeterminate after power-on reset, but are maintained during stop mode and non-POR resets. When using the in-circuit debugging features, the highest 19 bytes of the SRAM must be reserved for saved state storage and working space for the debugging routines.
MAX31782 User’s Guide 2.4.1 Program Memory Access The instructions that the MAX31782 is executing reside in what is defined as the program memory. The MMU fetches the instructions using the program bus. The instruction pointer (IP) register designates the program memory address of the next instruction to fetch. The IP register is read/write accessible by the user software. A write to the IP register forces program flow to the new address on the next cycle following the write.
MAX31782 User’s Guide PROGRAM SPACE FFFFh 1K x 16 SRAM A3FFh A000h 8FFFh 4K x 16 UTILITY ROM 8000h 7FFFh 16K x 16 FLASH (PAGE 1) 4000h 3FFFh 16K x 16 FLASH (PAGE 0) 0000h Figure 2-2.
MAX31782 User’s Guide 2.4.3.2 Frame Pointer The frame pointer (BP[OFFS]) is formed by the 16-bit unsigned addition of the 16-bit frame pointer base register (BP) and the 8-bit frame pointer offset register (OFFS). The method the MAX31782 uses to access data using the frame pointer is similar to the data pointers. When increments or decrements are used, only the value of OFFS is incremented or decremented.
MAX31782 User’s Guide 2.4.4.1 Memory Map When Executing from Flash Memory When executing from the flash memory: • Read and write operations of SRAM memory are executed normally. • The utility ROM can be read as data, starting at 8000h of the data space. The utility ROM cannot be written. Figure 2-3 illustrates the mapping of the SRAM and utility ROM memory segments into data memory space when code is executing from the flash memory segment.
MAX31782 User’s Guide 2.4.4.2 Memory Map When Executing from Utility ROM When executing from the utility ROM: • Read and write operations of SRAM memory are executed normally. • Reading of flash memory is executed normally. Writing to flash memory requires the use of the utility ROM routines. • One page (byte access mode) or both pages (word access mode) of the flash memory can be accessed as data with an offset of 8000h as determined by the CDA0 bit.
MAX31782 User’s Guide 2.4.4.3 Memory Map When Executing from SRAM When executing from the SRAM: The utility ROM can be read as data, starting at 8000h of the data space. The utility ROM cannot be written. Reading of flash memory is executed normally. Writing to flash memory requires the use of the utility ROM routines. One page (byte access mode) or both pages (word access mode) of the flash memory can be accessed as data with an offset of 0000h.
MAX31782 User’s Guide 2.5 Data Alignment To support merged program and data memory operation while maintaining efficient memory space usage, the data memory must be able to support both byte and word mode accessing. Data is aligned in data memory as words, but the effective data address is resolved to bytes. This data alignment allows program instruction fetching in words while maintaining data accessibility at the byte level.
MAX31782 User’s Guide POR BROWNOUT STATE CPU DISABLED ANALOG ACTIVE VDD > VBO VDD < VBO VDD < VBO VDD < VBO SYSTEM CLOCK STARTUP DELAY tSU:MOSC CPU MODE DIGITAL CORE ON ANALOG ON CODE IS EXECUTING PORT6 GPIO INT, I2C START INT, SVM INT OR EXT RESET CKCN.STOP = 1 STOP MODE DIGITAL CORE OFF ANALOG ON SVM MONITOR DEPENDS ON SVMEN AND SVMSTOP Figure 2-6. MAX31782 State Diagram 2.6.
MAX31782 User’s Guide 2.7 Clock Generation The MAX31782 generates its 4MHz instruction clock using an internal oscillator. This oscillator starts up when VDD exceeds the brownout voltage level, VBO. There is a delay of approximately 1000 clock cycles (tSU:MOSC) between when the oscillator starts and when clocking of the MAX31782 begins. This delay ensures that the clock is stable prior to beginning normal operation. 2.8 Power Modes The MAX31782 has two modes of operation.
MAX31782 User’s Guide SECTION 3: SYSTEM REGISTER DESCRIPTIONS This section contains the following information: 3.1 System Register Bit Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4 3.1.1 Accumulator Pointer Register (AP, 8h[0h]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MAX31782 User’s Guide SECTION 3: SYSTEM REGISTER DESCRIPTIONS Most MAX31782 functions are controlled by sets of registers. These registers provide a working space for memory operations as well as configuring and addressing peripheral registers on the device. Registers are divided into two major types: system registers and peripheral registers.
MAX31782 User’s Guide Table 3-2.
MAX31782 User’s Guide 3.1 System Register Bit Descriptions 3.1.1 Accumulator Pointer Register (AP, 8h[0h]) Initialization: This register is cleared to 00h on all forms of reset. Access: Unrestricted direct read/write access. BIT FUNCTION AP.[3:0] Active Accumulator Select. These bits select which of the 16 accumulator registers are used for arithmetic and logical operations.
MAX31782 User’s Guide 3.1.3 Processor Status Flags Register (PSF, 8h[4h]) Initialization: This register is cleared to 80h on all forms of reset. Access: Bit 7 (Z), bit 6 (S), and bit 2 (OV) are read-only. Bits 4 and 3 (GPF1, GPF0), bit 1 (C), and bit 0 (E) are unrestricted read/write. BIT FUNCTION PSF.0 (E) Equals Flag. This bit flag is set to 1 whenever a compare operation (CMP) returns an equal result. If a CMP operation returns not equal, this bit is cleared. PSF.1 (C) Carry Flag.
MAX31782 User’s Guide 3.1.5 Interrupt Mask Register (IMR, 8h[6h]) Initialization: This register is cleared to 00h on all forms of reset. Access: Unrestricted read/write access. The first six bits in this register are interrupt mask bits for modules 0 to 5, one bit per module. The eighth bit, IMS, serves as a mask for any system module interrupt sources. Setting a mask bit allows the enabled interrupt sources for the associated module or system (for the case of IMS) to generate interrupt requests.
MAX31782 User’s Guide 3.1.7 Interrupt Identification Register (IIR, 8h[Bh]) Initialization: This register is cleared to 00h on all forms of reset. Access: Read-only. The first six bits in this register indicate interrupts pending in modules 0 to 5, one bit per module. The eighth bit, IIS, indicates a pending system interrupt, such as from the watchdog timer. The interrupt pending flags are set only for enabled interrupt sources waiting for service.
MAX31782 User’s Guide 3.1.9 Watchdog Control Register (WDCN, 8h[Fh]) Initialization: Bits 5, 4, 3, and 0 are cleared to 0 on all forms of reset; for others, see individual bit descriptions. Access: Unrestricted direct read/write access. BIT FUNCTION WDCN.0 (RWT) Reset Watchdog Timer. Setting this bit to 1 resets the watchdog timer count.
MAX31782 User’s Guide 3.1.10 Accumulator n Register (A[n], 9h[nh]) Initialization: This register is cleared to 0000h on all forms of reset. Access: Unrestricted direct read/write access. BIT FUNCTION This register acts as the accumulator for all ALU arithmetic and logical operations when selected by the accumulator pointer (AP). It can also be used as a general-purpose working register. A[n].[15:0] 3.1.
MAX31782 User’s Guide 3.1.13 Stack Pointer Register (SP, Dh[1h]) Initialization: This register is cleared to 000Fh on all forms of reset. Access: Unrestricted direct read/write access. BIT FUNCTION SP.[3:0] These four bits indicate the current top of the hardware stack, from 0h to Fh. This pointer is incremented after a value is pushed on the stack and decremented before a value is popped from the stack. SP.[15:4] Reserved. All reads return 0. 3.1.
MAX31782 User’s Guide 3.1.18 Data Pointer Control Register (DPC, Eh[4h]) Initialization: This register is cleared to 001Ch on all forms of reset. Access: Unrestricted direct read/write access. BIT FUNCTION Source Data Pointer Select Bits 1:0. These bits select one of the three data pointers as the active source pointer for the load operation. A new data pointer must be selected before being used to read data memory: DPC.
MAX31782 User’s Guide 3.1.21 Frame Pointer Base Register (BP, Eh[7h]) Initialization: This register is cleared to 0000h on all forms of reset. Access: Unrestricted direct read/write access. BIT FUNCTION BP.[15:0] This register serves as the base pointer for the frame pointer (FP). The frame pointer is formed by unsigned addition of frame pointer base register (BP) and frame pointer offset register (OFFS).
MAX31782 User’s Guide 3.1.27 Data Pointer 1 Register (DP[1], Fh[7h]) Initialization: This register is cleared to 0000h on all forms of reset. Access: Unrestricted direct read/write access. BIT FUNCTION DP[1].[15:0] This register is used as a pointer to access data memory. DP[1] can be automatically incremented or decremented following each read operation, or can be automatically incremented or decremented before each write operation.
MAX31782 User’s Guide SECTION 4: PERIPHERAL REGISTER MODULES The MAX31782 has six peripheral register modules, Modules 0 through 5. This section describes the MAX31782’s peripheral registers. Table 4-1 shows the MAX31782 peripheral register map. Table 4-2 explains peripheral register bit functions. Detailed peripheral register bit descriptions and default values appear in the corresponding function block description section. Table 4-1.
INDEX 00h 01h 02h PD1 REGISTER I2CBUF_M I2CST_M I2CIE_M 1Ah TOEX — 18h 19h 17h ADCG1 ADCG5 16h ETS ADVOFF — 12h PD6 — 10h — — — — — EIES6 I2CCK_M 0Fh I2CCN_M — — I2CBUSY — — 14 — — 14 — 0Eh 0Ch 0Dh SVM I2CTO_M 09h PI6 — I2CBUS — — 15 C/TB — 15 I2CSLA_M 07h 08h EIE6 06h 11h PD2 EIF6 10h TB0CN 04h 0Dh TB0V 03h 0Bh PI1 PO6 09h PI2 MIIR1 07h 08h TB0R 06h TB0C 01h 03h PO1 00h PO2 MIIR0 INDEX REGISTER — — — — — — —
18h 19h 1Ah 1Bh 1Ch ICDT0 ICDT1 ICDC ICDF ICDB — — — — — — — 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h PWMCN0 PWMV1 PWMCN1 TACHV0 TACHCN0 TACHV1 TACHCN1 MIIR3 — — — — — — — TRPS[1:0] — — TRPS[1:0] — — — — — PWMCS PWMCS — — — PWMCR PWMCR — TPS[2:0] — TPS[2:0] PWMPS[2:0] PWMPS[2:0] — — 07h — PWMV0 — TACHR1 — 05h — TACHR0 — 04h — 03h SMBUS TF — TACHV1[15:0] TF TACHV0[15:0] TFB PWMV1[15:0] TFB PWMV0[15:0] TACHR1[15:0] TACHR0[15:0] PWMR
15h 16h 17h 18h PWMV5 PWMCN5 MIIR5 14h PWMC5 PWMR5 13h TACHCN5 11h TACHR5 12h 0Fh TACHR4 TACHV5 0Dh TACHCN4 — — — — — — TRPS[1:0] TRPS[1:0] — — PWMCS — — — PWMCR — — — — PWMPS[2:0] — TPS[2:0] TPS[2:0] PWMR4[15:0] 0Bh 0Ch PWMR4 PWMC4 TACHV4 PWMC4[15:0] 09h 0Ah PWMCN4 — TFB — PWMV5[15:0] PWMR5[15:0] PWMC5[15:0] TF TACHV5[15:0] TACHR5[15:0] TACHR4[15:0] TF TACHV4[15:0] TFB PWMV4[15:0] 07h 08h MC0R PWMV4 MC0[15:0] MC1[15:0] MC2[15:0] MB[15:
MAX31782 User’s Guide SECTION 5: INTERRUPTS This section contains the following information: 5.1 Servicing Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 5.2 Module Interrupt Identification Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MAX31782 User’s Guide SECTION 5: INTERRUPTS The MAX31782 provides a single, programmable interrupt vector (IV) that can be used to handle internal and external interrupts. Interrupts can be generated from system level sources (e.g., watchdog timer) or by sources associated with the peripheral modules. Only one interrupt can be handled at a time, and all interrupts naturally have the same priority.
MAX31782 User’s Guide SYSTEM MODULE WATCHDOG INTERRUPTS WDCN.WDIF WDCN.EWDI (LOCAL ENABLE) MODULE 1 IIR.IIS IMR.IMS MODULE ENABLE GPIO INTERRUPTS EXTERNAL INTERRUPT P6.0: EIF6.IFP6_0 LOCAL ENABLE EIE6.IEP6_0 EXTERNAL INTERRUPT P6.n: EIF6.IFP6_n LOCAL ENABLE EIE6.IEP6_n MASTER I2C INTERRUPTS MASTER I2C START INTERRUPT I2CST_M.I2CSRI LOCAL ENABLE I2CIE_M.I2CSRIE ANY I2C INTERRUPT I2CST_M.x IIR.II1 IMR.IM1 MODULE 1 ENABLE LOCAL ENABLE I2CIE_M.x IC.
MAX31782 User’s Guide Table 5-1. Interrupt Sources and Control Bits INTERRUPT Timer B: External Trigger Timer B: Overflow INTERRUPT FLAG TB0CN.EXFB TB0CN.TFB LOCAL ENABLE BIT MODULE INTERRUPT IDENTIFICATION BIT INTERRUPT IDENTIFICATION BIT MODULE ENABLE BIT TB0CN.ETB MIIR0.TB0 IIR.II0 IMR.IM0 IIR.II1 IMR.IM1 IIR.II2 IMR.IM2 IIR.II3 IMR.IM3 IIR.II4 IMR.IM4 IIR.II5 IMR.IM5 IIR.IIS IMR.IMS I2C Master START Interrupt I2CST_M.I2CSRI I2C Master Transmit Complete Interrupt I2CST_M.
MAX31782 User’s Guide 5.2 Module Interrupt Identification Registers The MIIR registers are implemented to indicate which particular function within a peripheral module has caused the interrupt. The MAX31782 has six peripheral modules, M0 to M5. An MIIR register is implemented in each peripheral module. The MIIR registers are 16-bit read-only registers and all of them default to 0000h on system reset. Each defined bit in an MIIR register is the final interrupt from a specific function, i.e.
MAX31782 User’s Guide 5.2.3 Peripheral Module 2 Interrupt Identification Register (MIIR2, M2[03h]) Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name — — — — — — — — — — — — — I2CS_WU I2CS ADC Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Access r r r r r r r r r r r r r r r r BIT NAME 15:3 — DESCRIPTION Reserved. A read returns 0. This bit is set when there is a wake-up interrupt from the I2C slave block.
MAX31782 User’s Guide 5.2.6 Peripheral Module 5 Interrupt Identification Register (MIIR5, M5[18h]) Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name — — — — — — — — — — — — — — TACH5 TACH4 Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Access r r r r r r r r r r R r r r r r BIT NAME 15:2 — DESCRIPTION 1 TACH5 This bit is set when there is an interrupt from tachometer 5 (TACH.5).
MAX31782 User’s Guide 5.3.2 Interrupt Prioritization by Software All interrupt sources of the MAX31782 naturally have the same priority. However, when CPU operation vectors to the programmed interrupt vector address, the order in which potential interrupt sources are interrogated is left entirely up to the user, as this often depends upon the system design and application requirements.
MAX31782 User’s Guide SECTION 6: ANALOG-TO-DIGITAL CONVERTER (ADC) This section contains the following information: 6.1 Detailed Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2 6.1.1 Conversion Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MAX31782 User’s Guide SECTION 6: ANALOG-TO-DIGITAL CONVERTER (ADC) The MAX31782 contains a 12-bit analog-to-digital converter (ADC) with a 7-input mux (Figure 6-1). The mux selects the ADC input from six external channels and one internal channel. The six external channels can operate in fully differential voltage mode or in single-ended voltage mode. In addition, any of the six external channels can be configured to measure the temperature of an external diode.
MAX31782 User’s Guide 6.1.2 Conversion Sequencing The MAX31782 ADC performs a user-defined sequence of up to eight conversions. Each conversion in a sequence is set up using one of the eight ADC configuration registers. The configuration registers are accessed by writing to the ADDATA register when ADST.ADCFG = 1. The configuration register pointed to by ADDATA is selected using the ADIDX bits in the ADST register.
MAX31782 User’s Guide Table 6-1.
MAX31782 User’s Guide 6.1.4 ADC Data Reading The ADC has a circular data buffer that holds the results from 16 conversions. This buffer is accessed by reading the ADDATA register when ADCFG is set to 0. The data buffer pointed to by ADST.ADIDX[3:0] is the buffer returned when ADDATA is read. ADIDX is automatically incremented following a read of ADDATA. This allows repeated reads of ADDATA to return the results from multiple conversions.
MAX31782 User’s Guide 6.2 ADC Register Descriptions The ADC is controlled by ADC SFR registers. Four of the registers, ADST, ADADDR, ADCN, and ADDATA, are used for setup, control, and reading from the ADC. There are five other registers, ETS, ADCG1, ADCG5, ADVOFF, and TOEX, which are used to adjust the gains and offsets applied to ADC results. To avoid undesired operations, the user should not write to bits labeled as reserved. 6.2.
MAX31782 User’s Guide 6.2.2 ADC Status Register (ADST) Register Address: M2[06h] Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name — — — — ADDAT3 ADDAT2 ADDAT1 ADDAT0 — ADCONV ADDAI ADCFG ADIDX3 ADIDX2 ADIDX1 ADIDX0 Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Access r r r r r r r r r rw rw rw rw rw rw rw BIT NAME 15:12 — 11:8 ADDAT[3:0] 7 — 6 DESCRIPTION Reserved. The user should not write to these bits.
MAX31782 User’s Guide 6.2.4 ADC Data and Configuration Register (ADDATA) Register Address: M2[09h] The ADDATA register is used to set up the ADC sequence configurations and also to read the results of the ADC conversions. If the ADST.ADCFG bit is set to 1, writing to ADDATA writes to one of the configuration registers. If ADST. ADCFG is set to 0, reading from ADDATA reads one of the conversion results. 6.2.4.
MAX31782 User’s Guide 3 ADDIFF ADC Differential Mode Select. In voltage mode, this bit selects the ADC conversion mode. When this bit is set to 1, the ADC conversion is in differential mode. When this bit is cleared to 0, the ADC conversion is performed in single-ended mode. During single-ended mode, the sample is measured between AD0P–AD5P and ground. If AD0P–AD5P transitions below 0, negative numbers are reported. No clamping of data is performed for negative inputs.
MAX31782 User’s Guide 6.2.5 External Temperature Slope Control Register (ETS) Register Address: M1[16h] Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name — — — — — — — — ETS7 ETS6 ETS5 ETS4 ETS3 ETS2 ETS1 ETS0 Reset 0 0 0 0 0 0 0 0 0 1 0 1 1 1 0 0 Access r r r r r r r r rw rw rw rw rw rw rw rw The ETS register changes the slope of external temperature measurements to compensate for changes in diode ideality factor.
MAX31782 User’s Guide 6.2.6 ADC External Temperature Offset Register (TOEX) Register Address: M1[1Ah] Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name S S S S 28 27 26 25 24 23 22 21 20 2-1 2-2 2-3 Reset s s s s s s s s s s s s s s s s Access rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw s = special, initial value is dependent on trim settings The TOEX register contains the temperature offset for the external temperature measurements.
MAX31782 User’s Guide 6.3 ADC Code Examples 6.3.1 One Sequence of Four Temperature and Voltage Conversions ADCN_bit.IREFEN = 1; //enable the internal reference ADST_bit.ADCFG = 1; //set ADDATA as ADCFG ADDATA = 0x08; //ADCFG[0]: Differential voltage CH0, 1.225V FS, Right Aligned ADDATA = 0x85; //ADCFG[2]: External temperature CH5, right aligned ADCN_bit.ADCONT = 0; ADST_bit.
MAX31782 User’s Guide 6.3.2 Continuous Conversion of 16 Samples ADCN_bit.IREFEN = 1; //enable the internal reference ADCN_bit.ADCONT = 1; //run continuous conversions ADCN_bit.ADDAINV = 3; //set the interrupt flag after 16 conversions ADST_bit.ADCFG = 1; //set ADDATA as ADCFG ADDATA = 0x08; //ADCFG[0]: Differential voltage, ch0, 1.225V FS, Right Aligned ADADDR = 0x0000; //ADSTART=0, ADEND=0, sequence is only ADCFG[0] ADST_bit.ADDAI = 0; //clear the interrupt flag while(!ADST_bit.
MAX31782 User’s Guide SECTION 7: I2C-COMPATIBLE SLAVE INTERFACE This section contains the following information: 7.1 Detailed Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-2 7.1.1 Default Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MAX31782 User’s Guide SECTION 7: I2C-COMPATIBLE SLAVE INTERFACE The MAX31782 provides an I2C-compatible slave controller that allows the MAX31782 to communicate with a host device. This controller can also operate as an SMBus slave. Also designed into the I2C slave controller is the ability to bootload the MAX31782 with new user flash memory. The I2C slave interface can be set up to provide system interrupts after each I2C event. Figure 7-1 shows the basic operation flow of the I2C slave controller.
MAX31782 User’s Guide 7.1.2 Slave Address Prior to communication, an I2C slave address may need to be selected. The I2C slave controller normally responds to two slave addresses. The I2C bootloader uses address 34h. This bootloader address cannot be changed and should not be used as the device slave address for normal communication. The second slave address is the address used for communication with the host. This slave address is set using the I2CSLA_S register.
MAX31782 User’s Guide RECEIVING SLAVE ADDRESS TRANSMITTING BYTE RECEIVING BYTE DETECT START I2CSRI = 1 I2CBUS = 1 I2CBUSY = 1 WRITE TO I2CBUF_S DETECT FIRST SCL RISING EDGE I2CBUSY = 1 I2CBUSY = 1 TRANSMIT SHIFT REGISTER BYTE, MSB FIRST RECEIVE A BIT INTO SHIFT REGISTER, MSB FIRST RECEIVE Addr[6:0] + R/W N MATCH I2CSLA_S? Y TRANSMIT I2CACK SET I2CMODE ACCORDING TO R/W I2CAMI = 1 I2CBUSY = 0 8 BITS RECEIVED? N 8 BITS TRANSMIT? Y RECEIVE ACKNOWLEDGE I2CNACKI = ACKNOWLEDGE I2CTXI = 1 I2CBUS
MAX31782 User’s Guide • Clears the I2CST_S.I2CBUSY flag to indicate that the I2C slave controller is not actively participating in the transfer of data. The detection of an ACK by the MAX31782 I2C slave controller indicates that the host wants to receive another byte of data. The I2C slave controller maintains control of SDA following the ACK. The next byte to transmit needs to be loaded into I2CBUF_S prior to the host starting to clock this next byte.
MAX31782 User’s Guide 7.1.8 Clock Stretching If a slave device cannot receive or transmit another complete byte of data, it can hold SCL low, forcing the master to wait. Data transfer continues when the slave is ready for another byte of data and releases SCL. The I2C slave controller can hold SCL low at the completion of each byte being transferred.
MAX31782 User’s Guide 7.1.9 SMBus Timeout The I2C slave controller can also be used for SMBus or PMBus™ communication. To maintain SMBus compatibility, a 30ms timer is implemented by the I2C slave controller. The purpose of this timer is to issue a timeout interrupt when SCL is low for greater than 30ms. The timer only starts when none of the following conditions are true: 1) The I2C slave controller is in the idle state and there is no communications on the I2C bus.
MAX31782 User’s Guide 7.2 I2C Slave Controller Register Descriptions The following registers are used to control the I2C slave interface, which uses the SDA and SCL pins. These registers control the I2C slave interface if it is operating as either a slave or master. The bit descriptions detail how to use these registers when operating in slave mode. When operating in master mode, some of the bits and registers have different functionality.
MAX31782 User’s Guide 7.2.2 I2C Slave Status Register (I2CST_S) Address: M2[01h] Bit Name 15 14 13 12 11 10 9 I2CBUS I2CBUSY — — I2CSPI I2CSCL I2CROI 8 7 I2CGCI I2CNACKI 6 5 4 3 2 1 0 — I2CAMI I2CTOI I2CSTRI I2CRXI I2CTXI I2CSRI Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Access r* r* r r rw r* rw rw rw* r rw rw rw* rw* rw rw *Set by hardware only. BIT NAME DESCRIPTION 15 I2CBUS I2C Slave Bus Busy.
MAX31782 User’s Guide 7.2.3 I2C Slave Interrupt Enable Register (I2CIE_S) Address: M2[02h] Bit 15 14 13 12 11 10 Name — — — — I2CSPIE — Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Access r r r r rw r rw rw rw r rw rw rw rw rw rw BIT NAME 15:12 — 11 I2CSPIE 10 — 9 8 7 I2CROIE I2CGCIE I2CNACKIE 6 5 — I2CAMIE 4 3 2 I2CTOIE I2CSTRIE I2CRXIE 1 0 I2CTXIE I2CSRIE DESCRIPTION Reserved. The user should not write to these bits.
MAX31782 User’s Guide 7.2.4 I2C Slave Address Register (I2CSLA_S) Address: M2[0Fh] Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name — — — — — — — — — A6 A5 A4 A3 A2 A1 A0 Reset 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 1 Access r r r R r r r r r rw rw rw rw rw rw rw BIT NAME 15:7 — 6:0 DESCRIPTION Reserved. The user should not write to these bits. A[6:0] These address bits contain the address of the I2C slave interface.
MAX31782 User’s Guide 7.2.6 SMBus Mode Selection Register (SMBUS) Address: M3[04h] Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 Name — — — — — — — — — — — — RESET_S RESET_M Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Access r r r r r r r r r r r r rw rw rw rw 1 0 SMB_MOD_S SMB_MOD_M This register contains bits that are used for both the I2C slave interface (SDA and SCL) and the I2C master interface (MSDA and MSCL).
MAX31782 User’s Guide SECTION 8: I2C-COMPATIBLE MASTER INTERFACE This section contains the following information: 8.1 Detailed Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2 8.1.1 Description of Master I2C Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MAX31782 User’s Guide SECTION 8: I2C-COMPATIBLE MASTER INTERFACE The MAX31782 provides an I2C-compatible master controller that allows the MAX31782 to communicate with a slave device. The I2C master interface can be setup to provide system interrupts after each I2C event. 8.1 Detailed Description 8.1.1 Description of Master I2C Interface The master I2C interface uses the MSDA and MSCL pins. These pins are the master I2C controller’s connection to the SDA and SCL pins of an I2C bus.
MAX31782 User’s Guide there is a rise time that is determined by the capacitive loading and pullup resistance on the SCL line. When the controller senses the SCL line has reached a high logic level, the count for SCL High Time begins. The same is true for a falling edge. The SCL Low Time only begins after the controller senses the SCL line at a low logic level.
MAX31782 User’s Guide 8.1.5 Generating a START To initiate a data transfer, the I2C master controller must first issue a START command. The master I2C controller’s flow when attempting to issue a START command is shown in Figure 8-3. A START command is generated by setting the I2CSTART bit to 1. The I2C controller monitors the status of SDA and SCL until it can generate a START condition.
MAX31782 User’s Guide When the I2CSTART bit is set to a 1, the I2C controller starts its timeout timer if enabled (I2CTO_M ≠ 0). If the timer expires before the START can be generated, t h e I2C timeout interrupt flag (I2CTOI) will be set and an interrupt generated if enabled. If a timeout occurs, the I2C master controller will reset to an idle state and the I2CSTART bit will be cleared.
MAX31782 User’s Guide Upon transmitting the slave data byte (7 bits of slave address + R/W bit + acknowledge), the I2C master controller will enter one of the three states. • Data Transmit: The I2CMODE (R/W) bit was set to a 0, indicating that the master will be writing data to a slave device. The MAX31782 will retain control of the SDA line. • Data Receive: The I2CMODE (R/W) bit was set to a 1, indicating that the master will be receiving data from a slave.
MAX31782 User’s Guide Following the 8th bit of data (least significant bit) being shifted to SDA, the SDA line will be released by the MAX31782 master controller. This allows the slave to signal an ACK or NACK during the 9th clock cycle. The MAX31782 I2C master controller samples the acknowledge bit following the 9th SCL rising edge.
MAX31782 User’s Guide If clock stretching is enabled after the 8th clock pulse, the master I2C controller will continue outputting the value of the I2CACK bit until clock stretching is released by clearing I2CSTRI. This allows software time to examine the data that was received prior to sending an ACK or NACK to the slave. The continuous output of I2CACK will occur even if the master I2C controller is transmitting data. In this mode, the slave should be sending the acknowledgement.
MAX31782 User’s Guide 8.2 I2C Master Controller Register Descriptions Following are the registers that are used to control the I2C master interface, which is the MSDA and MSCL pins. These registers are used to control the I2C master interface if it is operating as either a master or slave. The bit descriptions below detail how to use these registers when operating in master mode. When operating in slave mode, some of the bits and registers have different functionality.
MAX31782 User’s Guide 8.2.2 I2C Master Status Register (I2CST_M) Address: M1[01h] Bit 15 Name 14 I2CBUS I2CBUSY 13 12 11 10 9 8 7 6 5 4 3 2 1 0 — — I2CSPI I2CSCL I2CROI I2CGCI I2CNACKI — I2CAMI I2CTOI I2CSTRI I2CRXI I2CTXI I2CSRI Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Access r* r* r r rw r* rw rw rw* r rw rw rw* rw* rw rw *Set by hardware only. BIT NAME DESCRIPTION 15 I2CBUS I2C Master Bus Busy.
MAX31782 User’s Guide 8.2.3 I2C Master Interrupt Enable Register (I2CIE_M) Address: M1[02h] Bit 15 14 13 12 11 10 9 Name — — — — I2CSPIE — I2CROIE Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Access r r r r rw r rw rw rw r rw rw rw rw rw rw 8 7 6 I2CGCIE I2CNACKIE — 5 4 3 2 I2CAMIE I2CTOIE I2CSTRIE I2CRXIE 1 0 I2CTXIE I2CSRIE BIT NAME 15:12 — DESCRIPTION 11 I2CSPIE 10 — 9 I2CROIE I2C Master Receiver Overrun Interrupt Enable.
MAX31782 User’s Guide 8.2.5 I2C Master Clock Control Register (I2CCK_M) Address: M1[0Dh] Bit 15 Name 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 I2CCKH7 I2CCKH6 I2CCKH5 I2CCKH4 I2CCKH3 I2CCKH2 I2CCKH1 I2CCKH0 I2CCKL7 I2CCKL6 I2CCKL5 I2CCKL4 I2CCKL3 I2CCKL2 I2CCKL1 I2CCKL0 Reset 0 0 0 1 0 0 1 1 0 0 0 1 0 0 1 1 Access rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw BIT 15:8 7:0 NAME DESCRIPTION I2CCKH[7:0] These bits define the high period of the I2C clock.
MAX31782 User’s Guide 8.2.8 SMBus Mode Selection Register (SMBUS) Address: M3[04h] Bit 15 Name — 14 — 13 — 12 — 11 — 10 — 9 — 8 — 7 — 6 — 5 — 4 — Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Access r r r r r r r r r r r r rw rw rw rw 3 2 1 0 RESET_S RESET_M SMB_MOD_S SMB_MOD_M This register contains bits that are used for both the I2C slave interface (SDA and SCL) and the I2C master interface (MSDA and MSCL).
MAX31782 User’s Guide SECTION 9: PWM OUTPUTS This section contains the following information: 9.1 Detailed Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-3 9.1.1 PWM Pin Mapping and GPIO Muliplexing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MAX31782 User’s Guide SECTION 9: PWM OUTPUTS The MAX31782 provides six independent PWM output pins that can be used for power-supply margining or fan speed control. When the PWM output functionality of a pin is disabled, that pin can be used as a general-purpose input/output (GPIO). A diagram for one individual PWM output block is shown in Figure 9-1.
MAX31782 User’s Guide 9.1 Detailed Description 9.1.1 PWM Pin Mapping and GPIO Muliplexing Table 9-1 shows the mapping of each PWM Output. This table also shows that the PWM pins are mapped to GPIO port P1[5:0]. When a PWM output pin’s functionality is disabled (PWMCS = 0 or PWMCR = 0), the pin can be used as a GPIO. See SECTION 11: General-Purpose Input/Output (GPIO) Pins for information on using the PWM pins as GPIO. Table 9-1. PWM/GPIO Pin Multiplexing PWM OUTPUT PIN MAX31782 PIN NUMBER GPIO PIN PWM.
MAX31782 User’s Guide 9.1.3 Normal PWM Output Operation When operating in PWM output mode and configured for up count (DCEN = 0), the value in PWMVn is incremented until it reaches the reload value, PWMRn. At this point, PWMVn reloads with 0000h, the TFB flag is set (which can generate an interrupt if enabled), and counting continues. Figure 9-2 illustrates the PWM waveforms when the PWM is operating with DCEN = 0. The period of the PWM waveform is set by the value in the PWMRn register.
MAX31782 User’s Guide 9.1.4 Up/Down Count PWM Output Operation The PWM can also operate in an up/down count configuration by setting DCEN = 1. The value in PWMVn counts upward until it reaches the value in the reload register (PWMRn). On the next cycle the count reverses direction and starts counting down. When PWMVn reaches 0000h, the count again reverses direction and begins counting up.
MAX31782 User’s Guide 9.2 PWM Output Register Descriptions The following peripheral registers are used to control the PWM outputs of the MAX31782. Each of the six independent PWM outputs has four associated registers. Since there are six independent PWM outputs, the registers are described in a batch manner. For example, the control register is denoted as PWMCNn, where n = 0 to 5. Each PWM register is independent, meaning each PWM can be configured and operated differently. 9.2.
MAX31782 User’s Guide 9.2.2 PWM Value Register (PWMVn) The PWM value register, PWMVn, holds the 16-bit value of the PWM’s counter. Enabling or disabling the PWM with the PWMEN bit does not reset the PWMVn register. The PWMVn register must be cleared by software. This register is cleared to 0000h on all forms of reset and has unrestricted read/write access. 9.2.3 PWM Reload Register (PWMRn) The PWM reload register, PWMRn, is a 16-bit register that is used as a comparison to the PWMVn register.
MAX31782 User’s Guide SECTION 10: FAN TACHOMETER This section contains the following information: 10.1 Fan Tachometer Detailed Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-3 10.2 Timer/Fan Tachometer Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-3 10.
MAX31782 User’s Guide SECTION 10: FAN TACHOMETER The MAX31782 provides six independent fan tachometers that can be used to monitor the speed of six fans independently. When the fan tachometer functionality of a pin is disabled, that pin can be used as a general-purpose input/ output (GPIO). Figure 10-1 shows a diagram for one individual fan tachometer block. TPS[2:0] THIS DIAGRAM SHOWS ONE OF THE SIX INDEPENDENT TACHOMETERS.
MAX31782 User’s Guide 10.1 Fan Tachometer Detailed Description When a tachometer is initially enabled (TACHE = 1), it begins counting up from the TACHV value. The frequency of the counter is derived from the MAX31782’s 4MHz system clock (fMOSC). The tachometer can use a divided version of the system clock by using the timer prescaler (TPS[2:0] bits). When the TACHV count value reaches FFFFh, the counter rolls over to 0000h and continues counting.
MAX31782 User’s Guide 10.2.1 Tachometer Control Register (TACHCNn) The tachometer control register, TACHCNn, is used to set up and start the tachometer, and is also where tachometer interrupt flags are located. It should be noted that the user should not modify the reserved bits in the TACHCNn registers. Otherwise, undesired operation can occur. Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name — TRPS.1 TRPS.0 — — TPS.2 TPS.1 TPS.
MAX31782 User’s Guide 10.2.2 Tachometer Value Register (TACHVn) The tachometer value register, TACHVn, holds the 16-bit value of the tachometer’s up-counting timer. Enabling/disabling the tachometer with the TACHE bit does not reset this count value; it must be cleared explicitly by software. This register is cleared to 0000h on all forms of reset and has unrestricted read/write access. 10.2.
MAX31782 User’s Guide 10.4 Tachometer Code Example The following pseudocode shows how to set up tachometer 0. This example does not generate any interrupts, but instead the captured tachometer value can be periodically polled by software. Tachometer setup: TACHCN0_bit.TPS = 3; //tachometer clock is sysclk / 64 or 62.5kHz TACHCN0_bit.TEXEN = 1; //enable edge capture of TACH.0 pin TACHCN0_bit.TRPS = 1; TACHCN0_bit.
MAX31782 User’s Guide SECTION 11: GENERAL-PURPOSE INPUT/OUTPUT (GPIO) PINS This section contains the following information: 11.1 GPIO Port 1 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-4 11.1.1 GPIO Direction Register Port 1 (PD1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MAX31782 User’s Guide SECTION 11: GENERAL-PURPOSE INPUT/OUTPUT (GPIO) PINS The MAX31782 provides general-purpose input/output (GPIO) functionality on 21 pins. In addition to the GPIO functionality, each of these pins is multiplexed with at least one other function, which is classified as either a special function or alternate function. Special functions override the GPIO register settings of the port pin when they are enabled.
MAX31782 User’s Guide Table 11-1. GPIO Pins and Multiplexed Functions PIN NAME PORT INDEX ALTERNATE FUNCTION(S) ALTERNATE FUNCTION ENABLE SPECIAL FUNCTION SPECIAL FUNCTION ENABLE RESET STATE 28 PWM.0 P1.0 — — PWM.0 PWMCN0.PWMCR or PWMCS = 1 GPIO 26 PWM.1 P1.1 — — PWM.1 PWMCN1.PWMCR or PWMCS = 1 GPIO 24 PWM.2 P1.2 — — PWM.2 PWMCN2.PWMCR or PWMCS = 1 GPIO 20 PWM.3 P1.3 — — PWM.3 PWMCN3.PWMCR or PWMCS = 1 GPIO 18 PWM.4 P1.4 — — PWM.4 PWMCN4.
MAX31782 User’s Guide 11.1 GPIO Port 1 Register Descriptions Port 1 provides six GPIO pins that are multiplexed with PWM functionality. The PWM function is enabled when either the PWMCNn.PWMCR or PWMCS bits are a 1, where n = 0 to 5. If both of these bits are a 0, the pin operates as a GPIO. The port 1 pins provide all the functionality shown in the GPIO block diagram (Figure 11-1). This port does not provide GPIO interrupts. 11.1.
MAX31782 User’s Guide 11.2 GPIO Port 2 Register Descriptions Port 2 provides eight GPIO pins that are multiplexed with the tachometers and master I2C port. This port does not provide GPIO interrupts. The tachometer function is an alternate function. This means that the GPIO functions are fully supported, even when the pin is operating as a tachometer.
MAX31782 User’s Guide 11.3 GPIO Port 6 Register Descriptions Port 6 provides seven GPIO pins that are multiplexed with the test access port (TAP), Timer B, and slave I2C port. See Table 11-1 for more details about the multiplexed functions and how to enable or disable these functions. Note that SCL and SDA pins can be configured as GPIOs (P6.6 and P6.7, respectively) with open drain if needed, although this is not the typical application.
MAX31782 User’s Guide 11.3.3 GPIO Input Register for Port 6 (PI6) Bit 7 6 5 4 3 2 1 0 Name PI6_7 PI6_6 — PI6_4 PI6_3 PI6_2 PI6_1 PI6_0 Reset s s 1 s s s s s Access r r r r r r r r PI6 is an 8-bit register that contains the data that is applied to the GPIO pins. The PI6 input register contains valid input data even when the pin is not operating as a GPIO. The reset value for this register is dependent on the logical states applied to the pins.
MAX31782 User’s Guide 11.4 GPIO Code Example //set pin 6.4 as a high output PD6 |= 0x10; //set direction PD6.4 to 1 for an output PO6 |= 0x10; //set the output PO6.4 high //set pin 6.4 as a high-impedance input PD6 &= ~0x10; PO6 &= ~0x10; //set direction PD6.4 to 0 for input //set PO6.4 low to disable weak pullup //enable the pin 6.4 weak pullup PD6 &= ~0x10; PO6 |= 0x10; //set direction PD6.4 to 0 for input //set PO6.
MAX31782 User’s Guide SECTION 12: TIMER B MODULE This section contains the following information: 12.1 Detailed Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-2 12.1.1 Auto-Reload Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MAX31782 User’s Guide SECTION 12: TIMER B MODULE The MAX31782 provides one Timer B module that can be configured to provide different timer, counter, clock, or PWM functions. The Timer B uses the TBB and TBA pins, which are also used for JTAG and GPIO operation. Table 12-1 details these pins. Table 12-1. Timer B Pins TIMER B PIN MAX31782 PIN NUMBER GPIO PIN JTAG PIN TBA 33 P6.4 — TBB 35 P6.2 TMS 12.
MAX31782 User’s Guide 12.1.1 Auto-Reload Mode The 16-bit auto-reload mode of Timer B is established by clearing the CP/RLB bit to 0. In this mode, the timer performs a simple 16-bit timer or counter function that is reset to 0000h when a match between the Timer B count value register (TB0V) and the Timer B capture/reload register (TB0R) occurs. A block diagram of auto-reload mode is illustrated in Figure 12-1. If the C/TB bit is a logic 0, the timer’s input clock is a prescaled system clock.
MAX31782 User’s Guide 12.1.2 Up/Down Count with Auto-Reload The 16-Bit up/down count auto-reload mode is enabled by clearing the capture/reload bit (CP/RLB) to 0 and setting the down count enable bit (DCEN) to 1. This mode is illustrated in Figure 12-2. When DCEN is set to 1 the Timer B either counts up or down, depending upon the state of the TBB pin. If the TBB pin is high, the Timer B counts up and, if the TBB pin is low, the Timer B counts down. When DCEN = 0, the Timer B only counts up.
MAX31782 User’s Guide 12.1.3 Capture Mode The Timer B 16-bit capture mode is configured by setting the CP/RLB bit to 1. A block diagram of this mode is shown in Figure 12-3. In capture mode, the Timer B can be clocked either by a prescaled version of the system clock or falling edges of the TBA pin. When the timer is enabled in capture mode, it begins counting up from the value contained in the TB0V register until reaching an overflow state.
MAX31782 User’s Guide 12.1.4 Clock Output Mode The Timer B can be configured to drive a clock output on the TBA pin as shown in Figure 12-4. For the timer to operate in this mode, the capture/reload select bit (CP/RLB) and the counter/timer select bit (C/TB) must be cleared to 0 and the Timer B output enable bit (TBOE) must be set to 1. In this mode, the DCEN bit has no effect.
MAX31782 User’s Guide 12.1.5 PWM Output Mode The PWM output mode is enabled when the Timer B is enabled (TRB = 1) and either the TBCS or TBCR bit is set to 1. Table 12-3 describes how these bits determine the specific PWM operation. When operating as a PWM output, the Timer B can provide up to 16-bit resolution of the PWM frequency or duty cycle. The counter in the Timer B can operate as count up only, or count up/down. Table 12-3.
MAX31782 User’s Guide 12.1.5.1 Up Count PWM Output Mode When operating in PWM output mode and configured for up count (DCEN = 0), the value in TB0V is incremented until it reaches the reload value, TB0R. At this point, TB0V is reloaded with 0000h, the TFB flag is set (which can generate an interrupt if enabled), and counting continues. Figure 12-6 illustrates the PWM waveforms when the Timer B is operating in up count PWM output mode. The period of the PWM waveform is set by the value in the TB0R register.
MAX31782 User’s Guide 12.1.5.2 Up/Down Count PWM Output Mode The Timer B can also operate in an up/down count configuration when in PWM output mode by setting DCEN = 1. The timer counts upward until it reaches the value in the reload register (TB0R). On the next cycle, it reverses the count direction and starts counting down. When the TB0V counter reaches 0000h, it again reverses direction and begins counting up.
MAX31782 User’s Guide 12.2 Timer B Register Descriptions The following peripheral registers are used to control the Timer B timer and counter functions. Addresses of registers are given as “Mx[yy],” where x is the module number (from 0 to 5 decimal) and yy is the register index (from 00h to 1Fh hexadecimal). 12.2.
MAX31782 User’s Guide BIT NAME 5 TBOE Timer B Output Enable. Setting this bit to 1 enables the clock output function on the TBA pin if C/TB = 0. Clearing this bit to 0 allows the TBA pin to function as either a standard GPIO pin or a counter input for the Timer B. DCEN Down-Count Enable. In the compare modes, the DCEN bit controls whether the timer counts up and resets (DCEN = 0), or counts up and down (DCEN = 1).
MAX31782 User’s Guide 12.3 Timer B Code Examples 12.3.1 Auto-Reload Mode Creating a 10ms interrupt (10ms at 4MHz = 40,000 clock cycles): TB0R = 40000; //set the Reload Register TB0CN_bit.CPnRLB = 0; //clear for auto reload TB0V = 0x0000; TB0CN_bit.ETB = 1; TB0CN_bit.TRB = 1; //clear the Value Register //enable the interrupt //enable the Timer B operation 12.3.2 Clock Output Mode Creating a 100kHz clock on the TBA pin: TB0CN_bit.CPnRLB = 0; //clear for reload TB0CN_bit.
MAX31782 User’s Guide SECTION 13: SUPPLY VOLTAGE MONITOR The MAX31782 provides features to allow monitoring of its power supply. The supply voltage monitor (SVM) monitors the VDD power supply and can alert the processor through an interrupt if VDD falls below a programmable threshold. The MAX31782 provides the following power-monitoring features: • SVM compares VDD against a programmable threshold from approximately 2.7V to 5.3V.
MAX31782 User’s Guide SECTION 14: HARDWARE MULTIPLIER This section contains the following information: 14.1 Hardware Multiplier Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-2 14.2 Hardware Multiplier Controls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MAX31782 User’s Guide SECTION 14: Hardware Multiplier The hardware multiplier module can be used by the MAX31782 to support high-speed multiplications. The hardware multiplier module is equipped with two 16-bit operand registers, a 32-bit read-only result register, and an accumulator of 48-bit width. The multiplier can complete a 16-bit x 16-bit multiply-and-accumulate/subtract operation in a single cycle.
MAX31782 User’s Guide 14.2 Hardware Multiplier Controls The selection of operation to be performed by the multiplier is determined by four control bits in the MCNT register: SUS, MSUB, MMAC, and SQU. The number of operands that must be loaded to trigger the specified operation is dictated by the OPCS bit setting, except when the square function is enabled (SQU = 1).
MAX31782 User’s Guide most significant bit of the MC register occurs. For a signed two’s-complement multiply-accumulate/subtract operations, the OF bit is set when the carry-out/borrow-in from the most significant magnitude position of the MC register is different from the carryout/ borrow-in of the sign position of the MC register. Since there is no overflow condition for multiply and multiply-negate operations, the OF bit is always cleared for these operations with one exception.
MAX31782 User’s Guide 14.5 Hardware Multiplier Peripheral Registers The hardware multiplier registers are detailed in the following sections. Addresses of registers are given as “Mx[yy],” where x is the module number (from 0 to 5 decimal) and yy is the register index (from 00h to 1Fh hexadecimal). Table 14-2. Hardware Multiplier Registers REGISTER ADDRESS MCNT M5[00h] Multiplier Control Register. Selects operation, data type, operand count, hardware square function, and write option on the MC register.
MAX31782 User’s Guide 14.5.1 Multiplier Control Register (MCNT) Bit 7 6 5 4 3 2 1 0 Name OF MCW CLD SQU OPCS MSUB MMAC SUS Reset 0 0 0 0 0 0 0 0 Access r rw rw rw rw rw rw rw BIT NAME DESCRIPTION 7 OF Overflow Flag. This bit is set to logic 1 when an overflow occurred for the last operation. This bit can be set for accumulation/subtraction operations or unsigned multiply-negate attempts.
MAX31782 User’s Guide 14.5.2 Multiplier Operand A Register (MA) Bit Name 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MA.15 MA.14 MA.13 MA.12 MA.11 MA.10 MA.9 MA.8 MA.7 MA.6 MA.5 MA.4 MA.3 MA.2 MA.1 MA.0 Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Access rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Multiplier Operand A Register. This operand A register is used by the application code to load 16-bit values for multiplier operations. 14.5.
MAX31782 User’s Guide 14.5.7 Multiplier Read Register 1 (MC1R) Bit Name 15 14 13 12 11 10 MC1R.15 MC1R.14 MC1R.13 MC1R.12 MC1R.11 MC1R.10 9 8 7 6 5 4 3 2 1 0 MC1R.9 MC1R.8 MC1R.7 MC1R.6 MC1R.5 MC1R.4 MC1R.3 MC1R.2 MC1R.1 MC1R.
MAX31782 User’s Guide ;Signed Multiply-Accumulate 16-bit x 16-bit move MCNT, #02h move MB, #1001h move MA, #F001h ; MC2:0=0000_0100_0001h ; SUS=0 (signed) ; ; ; MC1R:MC0R= FF00_0003h ; MC2:0=0000_0000_0002h ;Unsigned Multiply-Subtract 16-bit x 16-bit move MCNT, #07h move MB, #1001h move MA, #0FFFh ; MC2:0=0000_0100_0001h ; MMAC=1, MSUB=1, SUS=1 (unsigned) ; ; ; MC1R:MC0R=FF00_0003h ; MC2:0=0000_0000_0002h ;Signed Multiply-Subtract 16-bit x 16-bit move MCNT, #06h move MB, #1001h move
MAX31782 User’s Guide SECTION 15: WATCHDOG TIMER This section contains the following information: 15.1 Watchdog Timer Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-3 15.1.2 Watchdog Timer Interrupt Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MAX31782 User’s Guide SECTION 15: WATCHDOG TIMER The watchdog timer is a user-programmable clock counter that can serve as a time-base generator, an event timer, or a system supervisor. As shown in Figure 15-1, the timer is driven by the main system clock and is supplied to a series of dividers. If the watchdog interrupt and the watchdog reset are disabled (WDCN.EWDI = 0 and WDCN.EWT = 0), the watchdog timer and its input clock are disabled.
MAX31782 User’s Guide 15.1 Watchdog Timer Description When the watchdog timer is enabled, it begins counting system clock cycles. The watchdog count is reset any time RWT is set to 1. If the watchdog count reaches the time interval set by WD[1:0], a watchdog timeout occurs, setting the watchdog interrupt flag (WDCN.WDIF). A watchdog timeout also generates an interrupt and/or reset to the MAX31782. Table 15-1 describes the possible states of the watchdog timer. Table 15-1.
MAX31782 User’s Guide 15.2.4 Watchdog Timer Control Register (WDCN) Bit Name 7 6 5 4 3 2 1 0 POR EWDI WD1 WD0 WDIF WTRF EWT RWT Reset s* s* 0 0 0 s* s* 0 Access rw rw rw rw rw rw rw rw *Bits 5, 4, 3 and 0 are cleared to 0 on all forms of reset; for others, see individual bit descriptions. BIT 7 6 NAME DESCRIPTION POR Power-On-Reset Flag. This bit is set to 1 whenever a power-on/brownout reset occurs. It is unaffected by other forms of reset.
MAX31782 User’s Guide SECTION 16: TEST ACCESS PORT (TAP) This section contains the following information: 16.1 TAP Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-3 16.2 TAP State Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MAX31782 User’s Guide SECTION 16: TEST ACCESS PORT (TAP) The MAX31782 incorporates a test access port (TAP) and TAP controller for communication with a host device across a 4-wire synchronous serial interface. The TAP can be used by the MAX31782 to support in-system programming and/ or in-circuit debug. The TAP is compatible with the JTAG IEEE standard 1149 and is formed by four interface signals as described in Table 16-1. For detailed information on the TAP and TAP controller, refer to IEEE STD 1149.
MAX31782 User’s Guide 16.1 TAP Controller The TAP controller is a synchronous state machine that responds to changes at the TMS and TCK signals. Based on its state transition, the controller provides the clock and control sequence for TAP operation. The performance of the TAP is dependent on the TCK clock frequency. The maximum TCK clock frequency should be limited to 1/8 the system clock frequency. This section provides a brief description of the state machine and its state transitions.
MAX31782 User’s Guide 16.2 TAP State Control The TAP provides an independent serial channel to communicate synchronously with the host system. The TAP state control is achieved through host manipulation of the test mode select (TMS) and test clock (TCK) signals. The TMS signal is sampled at the rising edge of TCK and decoded by the TAP controller to control movement between the TAP states. The TDI input and TDO output are meaningful once the TAP is in a serial shift state (i.e., Shift-IR or Shift-DR). 16.
MAX31782 User’s Guide When the parallel instruction register (IR2:0) is updated, the TAP controller decodes the instruction and performs any necessary operations, including activation of the data shift register to be used for the particular instruction during data register shift sequences (DR-Scan). The length of the activated shift register depends upon the value loaded to the instruction register (IR2:0).
MAX31782 User’s Guide 16.3 Communication via TAP The TAP controller is in Test-Logic-Reset state after a power-on reset. During this initial state, the instruction register contains the Bypass instruction and the serial path defined between the TDI and TDO pins for the Shift-DR state is the 1-bit bypass register. All TAP signals (TCK, TMS, TDI, and TDO) default to being weakly pulled high internally on any reset. The TAP controller remains in the Test-Logic-Reset state as long as TMS is held high.
MAX31782 User’s Guide TCK TMS TEST-LOGIC-RESET SELECT-IR-SCAN SELECT-DR-SCAN RUN-TEST/IDLE UPDATE-DR EXIT1-DR SHIFT-DR EXIT2-DR PAUSE-DR EXIT1-DR SHIFT-DR CAPTURE-DR SELECT-DR-SCAN RUN-TEST/IDLE CONTROL STATE TDI SHIFT REGISTER DON'T CARE OR UNDEFINED PARALLEL OUTPUT DON'T CARE OR UNDEFINED NEW DATA OLD DATA INSTRUCTION REGISTER DATA REGISTER DON'T CARE OR UNDEFINED TDO ENABLE TDO Figure 16-4.
MAX31782 User’s Guide SECTION 17: IN-CIRCUIT DEBUG MODE This section contains the following information: 17.1 Background Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-3 17.1.1 Breakpoint Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MAX31782 User’s Guide SECTION 17: IN-CIRCUIT DEBUG MODE The MAX31782 is equipped with embedded debug hardware and embedded ROM firmware developed for the purpose of providing in-circuit debugging capability to the user application. The in-circuit debug mode uses the JTAGcompatible Test Access Port (TAP) as its means of communication between the host and the MAX31782. Figure 17-1 shows a block diagram of the in-circuit debugger.
MAX31782 User’s Guide 9 MAX31782 0 X X TDI 9 0 TDO s1 HOST COMMAND/DATA INPUT MAX31782 DATA OUTPUT s0 STATUS Figure 17-2. 10-Bit Word Format Table 17-1. Status Bits s[1:0] STATUS/CONDITION 00 Non-Debug. Default condition, background mode, or debug engine inactive. 01 Debug Idle. Debug engine is ready to receive data from the host (command, data). 10 Debug Busy. Debug engine is busy without valid data (i.e., ROM code execution, trace operations). 11 Debug Valid.
MAX31782 User’s Guide Table 17-2. Background Mode Commands (continued) OP CODE COMMAND OPERATION 0000–0011 Read ICDA Read data from the ICDA. The contents of the ICDA register are loaded into the debug shift register through the ICDB register for host read. This command requires two follow-on transfer cycles with the least significant byte first. 0000–0100 Read ICDD Read data from the ICDD.
MAX31782 User’s Guide 17.1.1 Breakpoint Registers The MAX31782 incorporates six breakpoint registers (BP0–BP5) that are configurable by the host for establishing different types of breakpoint mechanisms. The first four breakpoint registers (BP0–BP3) are 16-bit registers that are configurable as program memory address breakpoints. When enabled, the debug engine forces a break when a match between the breakpoint register and the program memory execution address occurs.
MAX31782 User’s Guide 17.1.1.4 Breakpoint 3 Register (BP3) Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name BP3.15 BP3.14 BP3.13 BP3.12 BP3.11 BP3.10 BP3.9 BP3.8 BP3.7 BP3.6 BP3.5 BP3.4 BP3.3 BP3.2 BP3.1 BP3.0 Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Access s s s s s s s s s s s s s s s s s = special The breakpoint 3 register is accessible only via background mode read/write commands.
MAX31782 User’s Guide When REGE = 1: This register serves as one of the two register breakpoints. The destination module is indicated by the M[3:0] bits and the register within that module is defined by the R[4:0] bits. A break occurs when the following two conditions are met: 1) The destination register address for the executed instruction matches with the specified module and index.
MAX31782 User’s Guide Once in Debug mode, further breakpoint matches or host issuance of the Debug command are treated as no operations and do not disturb debug engine operation. Entering debug mode also stops the clocks to all timers, including the watchdog timer. Temporarily disabling these functions allows debug mode operations without disrupting the relationship between the original user program code and hardware timed functions.
MAX31782 User’s Guide Table 17-3. Debug Mode Commands OP CODE COMMAND OPERATION 0010–0000 No Operation No operation. 0010–0001 Read data from internal registers. This command forces the debug engine to update the CMD[3:0] bits in the ICDC to 0001b and perform a jump to ROM code at x8010h.
MAX31782 User’s Guide Table 17-3. Debug Mode Commands (continued) OP CODE COMMAND 0010–1000 Unlock the password lock. This command requires 32 follow-on transfer cycles each containing a byte value to be compared with the program memory password for the purpose of clearing the PWL Unlock pass- bit and granting access to protected debug and loader functions. When this command is received, word the debug engine updates the CMD[3:0] bit to 1000b and performs a jump to ROM code at x8010h.
MAX31782 User’s Guide Table 17-4.
MAX31782 User’s Guide Note that the trace operation uses a return address from the stack as a legitimate address for program fetching. The host must maintain consistency of program flow during the debug process. The Instruction Pointer is automatically incremented after each trace operation, thus a new return address is pushed onto the stack before returning the control to the debug engine.
MAX31782 User’s Guide 17.3 In-Circuit Debug Peripheral Registers The following peripheral registers are used to control the in-circuit debug mode of the MAX31782. Addresses of registers are given as “Mx[yy],” where x is the module number (from 0 to 5 decimal) and yy is the register index (from 00h to 1Fh hexadecimal). Fields in the bit definition tables are defined as follows: • Name: Symbolic names of bits or bit fields in this register.
MAX31782 User’s Guide 17.3.3 In-Circuit Debug Control Register (ICDC, M2[1Ah]) Bit 7 6 5 4 3 2 1 0 DME - REGE - CMD3 CMD2 CMD1 CMD0 Reset 0 0 0 0 0 0 0 0 Access rs r rs r rs rs rs rs Name r = read, s = special BIT NAME 7 DME 6 Reserved 5 REGE 4 Reserved DESCRIPTION Debug Mode Enable (DME). When this bit is cleared to 0, background mode commands may be executed, but breakpoints are disabled.
MAX31782 User’s Guide 17.3.4 In-Circuit Debug Flag Register (ICDF, M2[1Bh]) Bit 7 6 5 4 3 2 1 0 Name - - - - PSS1 PSS0 JTAG_SPE TXC Reset 0 0 0 0 0 0 0 0 Access r r r r rw rw rw rw r = read, s = special BIT NAME 7:4 Reserved DESCRIPTION Reserved. Do not write to these bits. Programming Source Select Bits [1:0].
MAX31782 User’s Guide 17.3.6 In-Circuit Debug Address Register (ICDA, M2[1Dh]) Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name ICDA.15 ICDA.14 ICDA.13 ICDA.12 ICDA.11 ICDA.10 ICDA.9 ICDA.8 ICDA.7 ICDA.6 ICDA.5 ICDA.4 ICDA.3 ICDA.2 ICDA.1 ICDA.0 Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Access r r r r r r r r r r r r r r r r This register is used by the debug engine to store addresses so that ROM code can view that information.
MAX31782 User’s Guide SECTION 18: IN-SYSTEM PROGRAMMING This section contains the following information: 18.1 Detailed Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-3 18.1.1 Password Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MAX31782 User’s Guide LIST OF FIGURES Figure 18-1. Entering Bootloader Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-3 Figure 18-2. I2C Bootloader Polling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-7 LIST OF TABLES Table 18-1.
MAX31782 User’s Guide SECTION 18: IN-SYSTEM PROGRAMMING The MAX31782 contains an internal bootstrap loader utilizing the JTAG or I2C interfaces. As a result, system software can be upgraded in-system, eliminating the need for a costly hardware retrofit when software updates are required. After each device reset, MAX31782 ROM code is executed which determines if bootloader operation is desired. Figure 18-1 provides information on how the MAX31782 enters into bootloader operation.
MAX31782 User’s Guide If SPE is not set, the MAX31782 then enables the slave I2C interface. The I2C_SPE bit in the I2C_SPB register is read to determine if I2C bootloader operation is desired. The I2C_SPB register is not cleared by a reset. See 18.1.3 Entering I2C Bootloader for more details on setting the I2C_SPE bit. If I2C_SPE is set, the MAX31782 sets the PSS[1:0] bits to 01, which designates I2C bootloader, and enters bootloader operation.
MAX31782 User’s Guide Following a reset, if the system programming buffer is set for JTAG bootloading, the bootload routine is entered. The host must now load the Debug instruction (010b) into the TAP instruction register (IR[2:0]), which enables the 10-bit Debug shift register between TDI and TDO.
MAX31782 User’s Guide 18.1.4 I2C System Programming Buffer Register (I2C_SPB) Bit 15 14 — 12 — 10 — 13 — 11 Name — — 9 — 8 — 7 — 6 — 5 — 4 — — 2 — 1 — Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Access r r r r r r r r r r r r r r r rw BIT NAME 15:1 — 0 3 0 I2C_SPE DESCRIPTION Reserved. The user should not write to these bits. Setting this bit to a 1, by writing to slave address 34h, denotes that I2C bootloading is desired upon exiting reset.
MAX31782 User’s Guide 4) Possibly poll returned data until command execution completes. 5) Transmit 00h on TDI for each Data Out byte. Read the Data Out byte on TDO. 6) Transmit 00h on TDI and verify that the Return byte output on TDO is 3Eh. 7) The Dummy RX byte is not required for the JTAG bootloader to operate. Some of the bootloader commands, such as the erase and CRC commands require extra time to execute. For these commands, the two status bits can be used to verify the state of the bootloader.
MAX31782 User’s Guide 18.3 Bootloader Commands Commands for the MAX31782 loader are grouped into families. All bootloader commands begin with a single command byte. The upper 4 bits of this command byte define the command family (from 0 to 15), while the lower 4 bits define the specific command within that family. The loader command families are shown in Table 18-5. Table 18-5.
MAX31782 User’s Guide 18.3.3 Command 02h—Master Erase Byte 1 Byte 2 Byte 3 Byte 4 Command NOP Return Dummy RX Input 02h 00h 00h 00h Output X X 3Eh X This command erases (sets to FFFFh) all words in the program flash memory and writes all words in the data SRAM to zero. This command is not password protected. After this command completes, the password lock bit is automatically cleared, allowing access to all bootloader commands. This command requires approximately 40 ms to complete.
MAX31782 User’s Guide Table 18-7. Bootloader Status Codes STATUS VALUE MEANING 00 No Error. The last command completed successfully. 01 Family Not Supported. An attempt was made to use a command from a family which the bootloader does not support. 02 Invalid Command. An attempt was made to use a nonexistent command within a supported command family. 03 No Password Match. An attempt was made to use a password-protected command without first matching a valid password.
MAX31782 User’s Guide 18.3.9 Command 08h—Get Loader Version Byte 1 Byte 2 Byte 3 Byte 4 Byte 5 Byte 6 Command NOP Data Out Data Out Return Dummy RX Input 08h 00h 00h 00h 00h 00h Output X X VersionL VersionH 3Eh X This command returns the device’s bootloader version. The format of the version is VersionH.VersionL. For example, if VersionL returns 00h and VersionH returns 01h, this corresponds to bootloader version 1.0. This command is not password protected. 18.3.
MAX31782 User’s Guide The JTAG bootloader also supports polling using the status bits as a method to determine when a word has successfully been written into flash. When sending the first two bytes of program data to load, the status bits should return as 11 to signify that the bootloader is valid. After sending the second byte, the bootloader begins writing this first word to flash and is busy.
MAX31782 User’s Guide 18.3.16 Command 30h—CRC Code Input Output Byte 1 Byte 2 Byte 3 Byte 4 Command Data In Data In Data In Byte 5 Byte 6 Data In Data In Byte 7 Byte 8 Byte 9 Byte 10 Byte 11 NOP Data Out Data Out Return Dummy RX 30h 2 AddrL AddrH LengthL LengthH 00h 00h 00h 00h 00h X X X X X X X CRCL CRCH 3Eh X This command returns the CRC-16 value (CRCH:CRCL) of the (LengthH:LengthL) bytes of program flash starting at (AddrH:AddrL).
MAX31782 User’s Guide 18.3.20 Command 50h—Load and Verify Code Input Output Byte 1 Byte 2 Byte 3 Byte 4 (Length) Bytes Byte Length+5 Byte Length+6 Byte Length+7 Command Data In Data In Data In Data In NOP Return Dummy RX 50h Length AddrL AddrH Data to load and verify 00h 00h 00h X X X X X X 3Eh X This command provides the combined functionality of the Load Code and Verify Code commands.
MAX31782 User’s Guide SECTION 19: PROGRAMMING This section contains the following information: 19.1 Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-2 19.2 Prefixing Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MAX31782 User’s Guide SECTION 19: PROGRAMMING The following section provides a programming overview of the MAX31782. For full details on the instruction set, as well as System Register and Peripheral Register detailed bit descriptions, see the appropriate sections in this user’s guide. 19.1 Addressing Modes The instruction set for the MAX31782 provides three different addressing modes: direct, indirect, and immediate.
MAX31782 User’s Guide does not require a prefixing operation even though the register DP[0] is 16-bit. This is because the prefix value defaults to zero, so the line move PFX[0], #00h is not required. 19.3 Reading and Writing Registers All functions in the MAX31782 are accessed through registers, either directly or indirectly. This section discusses loading registers with immediate values and transferring values between registers of the same size and different sizes. 19.3.
MAX31782 User’s Guide 19.3.4 Moving Values Between Registers of Different Sizes Before covering some transfer scenarios that might arise, a special register must be introduced that will be used in many of these cases. The 16-bit General Register (GR) is expressly provided for performing byte singulation of 16-bit words. The high and low bytes of GR are individually accessible in the GRH and GRL registers respectively.
MAX31782 User’s Guide High (16-bit destination) ← 8-bit source To modify only the high byte of a given 16-bit destination, the 16-bit register should be moved into the GR register such that the low byte can be singulated and the high byte can be written exclusively. Additional cycles are required if the destination index is greater than 0Fh or if the source index is greater than 0Fh.
MAX31782 User’s Guide 19.5 Using the Arithmetic and Logic Unit The MAX31782 provides a 16-bit ALU, which allows operations to be performed between the active accumulator and any other register. The MAX31782 provides 16 accumulator registers, of which any one may be selected as the active accumulator. 19.5.
MAX31782 User’s Guide • MOVE Acc, src (Copy data from source to active accumulator) • MOVE dst, Acc (Copy data from active accumulator to destination) • MOVE Acc, Acc (Recirculation of active accumulator contents) • XCHN (Exchange nibbles within each byte of active accumulator) • XCH (Exchange active accumulator bytes) The active accumulator may not be the source in any instruction where it is also the implicit destination.
MAX31782 User’s Guide For this example, assume that all 16 accumulator registers are initially set to zero. move move AP, #02h APC, #02h ; select A[2] as active accumulator ; auto-increment AP[1:0] modulo 4 ; AP A[0] A[1] A[2] A[3] ; 02 0000 0000 0000 0000 add #01h ; 03 0000 0000 0001 0000 add #03h ; 01 0003 0000 0001 0002 add add add #02h #04h #05h ; ; ; 00 02 03 0000 0003 0003 0000 0004 0004 0001 0001 0006 0002 0002 0002 19.5.
MAX31782 User’s Guide 19.5.5 ALU Bit Operations Using Only the Active Accumulator The following operations operate on single bits of the current active accumulator in conjunction with the Carry flag. Any of these operations may use an Acc bit from 0 to 15. move C, Acc.0 ; copy bit 0 of accumulator to Carry move Acc.5, C ; copy Carry to bit 5 of accumulator and Acc.3 ; Acc.3 = Acc.3 AND Carry or Acc.0 ; Acc.0 = Acc.0 OR Carry xor Acc.1 ; Acc.1 = Acc.
MAX31782 User’s Guide 19.6.3 Equals Flag The Equals flag (PSF.0) is a static flag set by the CMP instruction. When the source given to the CMP instruction is equal to the active accumulator, the Equals flag is set to 1. When the source is different from the active accumulator, the Equals flag is cleared to 0. The following instructions use the value of the Equals flag. Please note that the ‘src’ for the JUMP E/NE instructions must be immediate.
MAX31782 User’s Guide 19.6.5 Overflow Flag The Overflow flag (PSF.2) is a static flag indicating that the carry or borrow bit (Carry status Flag) resulting from the last ADD/ADDC or SUB/SUBB operation but did not match the carry or borrow of the high order bit of the active accumulator. The overflow flag is useful when performing signed arithmetic operations.
MAX31782 User’s Guide 19.7.3 Conditional Jumps Conditional jumps transfer program execution based on the value of one of the status flags (C, E, Z, S). Except where noted for JUMP E and JUMP NE, the absolute and relative operands allowed are the same as for the unconditional JUMP command.
MAX31782 User’s Guide 19.7.5 Looping Operations Looping over a section of code can be performed by using the conditional jump instructions. However, there is built-in functionality, in the form of the ‘DJNZ LC[n], src’ instruction, to support faster, more compact looping code with separate loop counters. The 16-bit registers LC[0], and LC[1] are used to store these loop counts.
MAX31782 User’s Guide 19.7.6 Conditional Returns Similar to the conditional jumps, the MAX31782 also supports a set of conditional return operations. Based upon the value of one of the status flags, the CPU can conditionally pop the stack and begin execution at the address popped from the stack. If the condition is not true, the conditional return instruction does not pop the stack and does not change the instruction pointer.
MAX31782 User’s Guide To support high priority interrupts while servicing another interrupt source, the IMR register may be used to create a user-defined prioritization. The IMR mask register should not be utilized when the highest priority interrupt is being serviced because the highest priority interrupt should never be interrupted. This is default condition when a hardware branch is made the Interrupt Vector address (INS is set to 1 by hardware and all other interrupt sources are blocked).
MAX31782 User’s Guide 19.9 Accessing the Stack The hardware stack is used automatically by the CALL, RET and RETI instructions, but it can also be used explicitly to store and retrieve data. All values stored on the stack are 16 bits wide. The PUSH instruction increments the stack pointer SP and then stores a value on the stack. When pushing a 16-bit value onto the stack, the entire value is stored.
MAX31782 User’s Guide Either of the data pointers may be post-incremented or post-decremented following any read or may be pre-incremented or predecremented before any write access by using the following syntax.
MAX31782 User’s Guide Once the pointer selection has been made, it remains in effect until: • The source data pointer select bits are changed via the explicit or implicit methods described above (i.e., another data pointer is selected for use). • The memory to which the active source data pointer is addressing is enabled for code fetching using the Instruction Pointer. Or, • A memory write operation is performed using a data pointer other than the current active source pointer.
MAX31782 User’s Guide SECTION 20: INSTRUCTION SET SUMMARY Table 20-1.
MAX31782 User’s Guide Table 20-1.
MAX31782 User’s Guide ADD/ADDC src Add/Add with Carry Description: The ADD instruction sums the active accumulator (Acc or A[AP]) and the specified src data and stores the result back to the active accumulator. The ADDC instruction additionally includes the Carry (C) Status Flag in the sum- mation. For the complete list of src specifiers, reference the MOVE instruction. Because the source field is limited to 8 bits, the PFX[n] register is used to supply the high-byte of data for 16 bit sources.
MAX31782 User’s Guide AND src Logical AND Description: Performs a logical-AND between the active accumulator (Acc) and the specified src data. For the complete list of src specifiers, reference the MOVE instruction. Because the source field is limited to 8 bits, the PFX[n] register is used to supply the high-byte of data for 16 bit sources.
MAX31782 User’s Guide {L/S}CALL src {Long/Short} Call to Subroutine Description: Performs a call to the subroutine destination specified by src. The CALL instruction uses an 8-bit immediate src to perform a relative short call (IP +127/-128 words). The CALL instruction uses a 16-bit immediate src to perform an absolute long CALL to the specified 16-bit address. The PFX[0] register is used to supply the high byte of a 16-bit immediate address for the absolute long CALL. Using the optional ‘L’ prefix (i.e.
MAX31782 User’s Guide CMP src Compare Accumulator Description: Compare for equality between the active accumulator and the least significant byte of the specified src. Because the source is limited to 8 bits, the PFX[n] register is used to supply the high-byte of data for 16 bit sources.
MAX31782 User’s Guide CPL C Complement Carry Flag Description: Logically complements the Carry (C) Flag. Status Flags: C Operation: C ← ~C Encoding: 15 1101 1010 0010 0 1010 ;C=0 Example(s): ;C←1 CPL C {L/S}DJNZ LC[n], src Decrement Counter, {Long/Short} Jump Not Zero Description: The DJNZ LC[n], src instruction performs a conditional branch based upon the associated Loop Counter (LC[n]) reg- ister.
MAX31782 User’s Guide {L/S} JUMP src Unconditional {Long/Short} Jump Description: Performs an unconditional jump as determined by the src specifier. The JUMP instruction uses an 8-bit immediate src to perform a relative jump (IP +127/-128 words). The JUMP instruction uses a 16-bit immediate src to perform an absolute JUMP to the specified 16-bit address. The PFX[0] register is used to supply the high byte of a 16-bit immediate address for the absolute JUMP. Using the optional ‘L’ prefix (i.e.
MAX31782 User’s Guide Conditional {Long/Short} Jump on Status Flag {L/S}JUMP C/{L/S}JUMP NC, src, L/S}JUMP Z/{L/S}JUMP NZ, src, {{L/S}JUMP E/{L/S}JUMP NE, src, {L/S}JUMP S, src Description: Performs conditional branching based upon the state of a specific processor status flag. JUMP C results in a branch if the Carry flag is set while JUMP NC branches if the Carry flag is clear. JUMP Z results in a branch if the Zero flag is set while JUMP NZ branches if the Zero flag is clear.
MAX31782 User’s Guide Z=0: IP ← IP + src (relative) -or- src (absolute) JUMP NZ Operation: Z=1: IP ← IP + 1 Encoding: 15 f101 1100 Example(s): JUMP NZ, label1 ssss 0 ssss ; Z=1, branch taken JUMP E E=1: IP ← IP + src (relative) -or- src (absolute) Operation: E=0: IP ← IP + 1 Encoding: 15 0011 1100 ssss 0 ssss Example(s): JUMP E, label1 ; E=1, branch taken Special Notes: The src specifier must be immediate data.
MAX31782 User’s Guide MOVE dst, src Move Data Description: Moves data from a specified source (src) to a specified destination (dst). A list of defined source, destination spec- ifiers is given in the table below. Also, since src can be either 8-bit (byte) or 16-bit (word) data, the rules governing data transfer are also explained below in the encoding section.
MAX31782 User’s Guide MOVE dst, src (continued) Move Data Table 20-3. Destination Specifier Codes dst dst Bit Encoding (ddd dddd) WIDTH (16 OR 8) NUL 111 0110 8/16 Null (Virtual) Destination. Intended as a bit bucket to assist software with pointer increments/decrements. MN[n] nnn 0NNN 8/16 nnnn Selects One of First 8 Registers in Module NNN; where NNN= 0 to 5. Access to Next 24 Using PFX[n].
MAX31782 User’s Guide Example(s): MOVE A[0], A[3] ; A[0] ← A[3] MOVE DP[0], #110h ; DP[0] ← #0110h (PFX[0] register used) ; MOVE PFX[0], #01h (smart-prefixing) ; MOVE DP[0], #10h MOVE DP[0], #80h ; DP[0] ← #0080h (PFX[0] register not needed) Special Notes: Proper loading of the PFX[n] registers, when for the purpose of supplying 16-bit immediate data or accessing 2-cycle destinations, is handled automatically by the assembler and is therefore an optional step for the user when writing asse
MAX31782 User’s Guide MOVE C, Acc. Move Accumulator Bit to Carry Flag Description: Replaces the Carry (C) status flag with the specified active accumulator bit. Status Flags: C Operation: C ← Acc. Encoding: 15 1110 1010 bbbb 0 1010 ; Acc = 01C0h, C=0 Example(s): MOVE C, Acc.8 ; C =1 MOVE C, src. Move Bit to Carry Flag Description: Replaces the Carry (C) status flag with the specified source bit src.. Status Flags: C Operation: C ← src.
MAX31782 User’s Guide MOVE C, #1 Set Carry Flag Description: Sets the Carry (C) processor status flag. Status Flag: C←1 Operation: C←1 Encoding: 15 1101 1010 0001 0 1010 ;C=0 Example(s): ;C←1 MOVE C, #1 MOVE dst., #0 Clear Bit Description: Clears the bit specified by dst.. Status Flags: C, E (if dst is PSF), S, Z Operation: dst. ← 0 Encoding: 15 1ddd dddd 0111 ; M0[0] = FEh Example(s): Special Notes: 0bbb 0 MOVE M0[0].1, #0 ; M0[0] = FCh MOVE M0[0].
MAX31782 User’s Guide NEG Negate Accumulator Description: Performs a negation (two’s complement) of the active accumulator and returns the result back to the active accumulator. Status Flags: S, Z Operation: Acc ← ~Acc + 1 Encoding: 15 1000 1010 1001 0 1010 ; Acc = FEEDh, S=1, Z=0 Example(s): NEG ; Acc = 0113h, S=0, Z=0 OR src Logical OR Description: Performs a logical-OR between the active accumulator (Acc or A[AP]) and the specified src data.
MAX31782 User’s Guide OR Acc. Logical OR Carry Flag with Accumulator Bit Description: Performs a logical-OR between the Carry (C) status flag and a specified bit of the active accumulator (Acc.) and returns the result to the Carry. Status Flags: C Operation: C ← C OR Acc. Encoding: 15 1010 1010 bbbb 0 1010 ; Acc = 2345h, C=0 at start Example(s): OR Acc.1 ; Acc.1=0 → C=0 OR Acc.2 ; Acc.
MAX31782 User’s Guide POPI dst Pop Word from the Stack Enable Interrupts Description: Pops a single word from the stack (@SP) to the specified dst and decrements the stack pointer (SP). Additionally, POPI returns the interrupt logic to a state in which it can acknowledge additional interrupts.
MAX31782 User’s Guide RET Return from Subroutine Description: RET pops a single word from the stack (@SP) into the Instruction Pointer (IP) and decrements the stack pointer (SP). The decremented SP is saved as the new stack pointer (SP). Status Flags: None Operation: IP ← @ SP-- Encoding: 15 1000 Example(s): 1100 0000 0 1101 RET Code Execution: Addr (IP) Op Code 0311h ... 0312h RET 0103h ...
MAX31782 User’s Guide RET NC C=0: IP ← @SP-- Operation: C=1: IP ← IP +1 15 Encoding: 1110 1100 RET NC Example(s): 0000 0 1101 ; C=1, return (RET) does not occur RET Z Z=1: IP ← @SP-- Operation: Z=0: IP ← IP + 1 15 Encoding: 1001 1100 RET Z Example(s): 0000 0 1101 ; Z=0, return (RET) does not occur RET NZ Z=0: IP ← @SP-- Operation: Z=1: IP ← IP +1 15 Encoding: 1101 1100 RET NZ Example(s): 0000 0 1101 ; Z=0, return (RET) is performed RET S S=1: IP ← @SP-- Operation: S=
MAX31782 User’s Guide RETI Return from Interrupt Description: RETI pops a single word from the stack (@SP) into the Instruction Pointer (IP) and decrements the stack pointer (SP). Additionally, RETI returns the interrupt logic to a state in which it can acknowledge additional interrupts.
MAX31782 User’s Guide RETI Z Z=1: IP ← @SP-- Operation: INS ← 0 Z=0: IP ← IP + 1 15 Encoding: 1001 1100 RETI Z Example(s): 1000 0 1101 ; Z=0, return from interrupt (RETI) does not occur RETI NZ Z=0: IP ← @SP-- Operation: INS ← 0 Z=1: IP ← IP +1 15 Encoding: 1101 1100 RETI NZ Example(s): 1000 0 1101 ; Z=0, return from interrupt (RETI) is performed RETI S S=1: IP ← @SP-- Operation: INS ← 0 S=0: IP ← IP + 1 15 Encoding: 1100 RETI S Example(s): 1100 1000 0 1101 ; S=0, ret
MAX31782 User’s Guide RL/RLC Rotate Left Accumulator Carry Flag (Ex/In)clusive Description: Rotates the active accumulator left by a single bit position. The RL instruction circulates the msb of the accumula- tor (bit 15) back to the lsb (bit 0) while the RLC instruction includes the Carry (C) flag in the circular left shift. Status Flags: C (for RLC only), S, Z (for RLC only) RL Operation: 15 Active Accumulator (Acc) 0 Acc.[15:1] ← Acc.[14:0]; Acc.0 ← Acc.
MAX31782 User’s Guide RR/RRC Rotate Right Accumulator Carry Flag (Ex/In)clusive Description: Rotates the active accumulator right by a single bit position. The RR instruction circulates the lsb of the accumula- tor (bit 0) back to the msb (bit 15) while the RRC instruction includes the Carry (C) flag in the circular right shift. Status Flags: C (for RRC only), S, Z (for RRC only) RR Operation: 15 Active Accumulator (Acc) 0 Acc.[14:0] ← Acc.[15:1]; Acc.15 ← Acc.
MAX31782 User’s Guide SLA/SLA2/SLA4 Shift Accumulator Left Arithmetically One, Two, or Four Times Description: Shifts the active accumulator left once, twice, or four times respectively for SLA, SLA2, and SLA4. For each shift iter- ation, a 0 is shifted into the lsb, and the msb is shifted into the Carry (C) flag. For signed data, this shifting process effectively retains the sign orientation of the data to the point at which overflow/underflow would occur.
MAX31782 User’s Guide SR/SRA/SRA2/SRA4 Shift Accumulator Right/Shift Accumulator Right Arithmetically One, Two, or Four Times Description: Shifts the active accumulator right once for the SR, SRA instructions and 2 or 4 times, respectively, for the SRA2, SRA4 instructions. The SR instruction shifts a 0 into the accumulator msb while the SRA, SRA2, and SRA4 instruc- tions effectively shift a copy of the current msb into the accumulator, thereby preserving any sign orientation.
MAX31782 User’s Guide 15 SRA2 Operation: Active Accumulator (Acc) 0 Carry Flag Acc.[13:0] ← Acc.[15:2] Acc.[15:14] ← Acc.15 C ← Acc.1 15 Encoding: 1000 1010 1110 0 1010 ; Acc = 0003h, C=0, Z=0 Example(s): SRA2 ; Acc = 0000h, C=1, Z=1 15 SRA4 Operation: Active Accumulator (Acc) 0 Carry Flag Acc.[11:0] ← Acc.[15:4] Acc.[15:12] ← Acc.15 C ← Acc.
MAX31782 User’s Guide SUB/SUBB src Subtract /Subtract with Borrow Description: Subtracts the specified src from the active accumulator (Acc) and returns the result back to the active accumula- tor. The SUBB additionally subtracts the borrow (Carry Flag), which may have resulted from previous subtraction. For the complete list of src specifiers, reference the MOVE instruction. Because the source is limited to 8 bits, the PFX[n] register is used to supply the highbyte of data for 16 bit sources.
MAX31782 User’s Guide XCH Exchange Accumulator Bytes Description: Exchanges the upper and lower bytes of the active accumulator. Status Flags: S Operation: Acc.[15:8] ← Acc.[7:0] Acc.[7:0] ← Acc.[15:8] Encoding: 15 1000 1010 1000 0 1010 ; Acc = 2345h Example(s): XCHN ; Acc = 4523h XCHN Exchange Accumulator Nibbles Description: Exchanges the upper and lower nibbles in the active accumulator byte(s). Status Flags: S Operation: Acc.[7:4] ← Acc.[3:0] Acc.[3:0] ← Acc.[7:4] Acc.
MAX31782 User’s Guide XOR src Logical XOR Description: Performs a logical-XOR between the active accumulator (Acc or A[AP]) and the specified src data. For the complete list of src specifiers, reference the MOVE instruction. Because the source is limited to 8 bits, the PFX[n] register is used to supply the high-byte of data for 16 bit sources.
MAX31782 User’s Guide SECTION 21: UTILITY ROM This section contains the following information: 21.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-2 21.2 In-Application Programming Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MAX31782 User’s Guide SECTION 21: UTILITY ROM 21.
MAX31782 User’s Guide 21.2 In-Application Programming Functions 21.2.1 UROM_flashWrite Function UROM_flashWrite Summary Programs a single word of flash memory Inputs A[0]: Word address in program flash memory to write. A[1]: Value to write to flash memory. Outputs Carry: Set on error and cleared on success Destroys PSF, LC[1] Notes: • This function uses two stack levels to save and restore values. • If the watchdog reset function is active, it should be disabled before calling this function.
MAX31782 User’s Guide 21.3 Data Transfer Functions The MAX31782 cannot access data from the same memory segment that is currently being used for instructions. For example, when instructions are executing from FLASH, data in FLASH cannot be accessed. The following utility ROM functions can be used to transfer data from one memory segment to another. For example, if data in FLASH needs to be copied to SRAM, one of these ROM functions can be called to do this transfer.
MAX31782 User’s Guide 21.3.1 UROM_moveDP0 Function UROM_moveDP0 Summary Reads the byte/word value pointed to by DP[0]. Inputs DP[0]: Address to read from data space (include 8000h offset if reading from flash). Outputs GR: Data byte/word read. Destroys None Notes: • Before calling this function, DPC should be set appropriately to configure DP[0] for byte or word mode. • The address passed to this function should be based on the data memory mapping for the utility ROM, as shown in Figure 21-1.
MAX31782 User’s Guide 21.3.4 UROM_moveDP1 Function UROM_moveDP1 Summary Inputs Reads the byte/word value pointed to by DP[1]. Outputs GR: Data byte/word read. Destroys None DP[1]: Address to read from data space (include 8000h offset if reading from flash). Notes: • Before calling this function, DPC should be set appropriately to configure DP[1] for byte or word mode. • The address passed to this function should be based on the data memory mapping for the utility ROM, as shown in Figure 21-1.
MAX31782 User’s Guide 21.3.7 UROM_moveBP Function UROM_moveBP Summary Reads the byte/word value pointed to by BP[OFFS]. Inputs BP[OFFS]: Address to read from data space (include 8000h offset if reading from flash). Outputs GR: Data byte/word read Destroys None. Notes: • Before calling this function, DPC should be set appropriately to configure BP[OFFS] for byte or word mode.
MAX31782 User’s Guide 21.3.10 UROM_copyBuffer Function UROM_copyBuffer Summary LC[0] bytes/words (up to 256) from DP[0] to BP[OFFS]. Inputs DP[0]: Starting address to copy from. BP[OFFS]: Starting address to copy to. LC[0]: Number of bytes/words to copy. Outputs OFFS is incremented by LC[0]. DP[0] is incremented by LC[0]. Destroys LC[0] Notes: • This function can be used to copy from program flash to data RAM, or from one part of data RAM to another.
MAX31782 User’s Guide 21.4 Utility ROM Examples 21.4.
MAX31782 User’s Guide REVISION HISTORY REVISION NUMBER REVISION DATE 0 8/11 DESCRIPTION Initial release PAGES CHANGED — Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits) shown in the Electrical Characteristics table are guaranteed.
