Datasheet

MAX31782
System Management Microcontroller
15
PWM Outputs
The device provides six independent PWM outputs. Each
PWM output is associated with four SFRs: PWMCNn,
PWMVn, PWMRn, and PWMCn, where n = 0–5 is the
channel number. The PWM clock is derived from the
system clock with a division ratio defined by PWMCNn.
The PWMCNn register also enables/disables the PWM
output and selects the PWM polarity. The user can set
the frequency and the duty cycle of each PWM output
individually by configuring the corresponding PWMRn
register and the PWMCn register, respectively.
When the PWM output functionality of a PWM.n pin is
disabled, that pin can be used as a GPIO. When used
as GPIO pins, PWM.n pins are accessed as Port 1 and
through three SFRs: PO1, PI1, and PD1. Each PWM.n pin
can be independently configured, and can be defined
as an input with weak pullup, an input without pullup, or
an output.
Table 2. I/O Port Pins
Figure 4. Port 6 I/O Block Diagram
PD6.n
SF DIRECTION
SF ENABLE
MUXMUX
PO6.n
V
DD
SF OUTPUT
V
DD
WEAK
I/O PAD
P6.n
INTERRUPT
FLAG
FLAG
PI6.n OR SF INPUT
n = 0−4
EIES6.n
DETECT
CIRCUIT
EIE6.n
MAX31782
PORT INDEX
PRIMARY
FUNCTION
ALTERNATE
FUNCTION
INTERRUPTS TAP (JTAG) RESET STATE
P6.0 GPIO, P6.0 — INT0 TCK TCK
P6.1 GPIO, P6.1 — INT1 TDI TDI
P6.2 GPIO, P6.2 Timer B TBB Pin INT2 TMS TMS
P6.3 GPIO, P6.3 — INT3 TDO TDO
P6.4 GPIO, P6.4 Timer B TBA Pin INT4 —
GPIO input with
weak pullup