Datasheet

MAX31782
System Management Microcontroller
5
ELECTRICAL CHARACTERISTICS: JTAG INTERFACE
(V
DD
= 2.7V to 5.5V, T
A
= -40NC to +85NC, unless otherwise noted.) (Figure 2)
Note 1: All voltages are referenced to ground (V
SS
). Currents entering the IC are specified positive and currents exiting the IC are
negative.
Note 2: This value does not include current in SDA, SCL, and P6.0–P6.4.
Note 3: Guaranteed by design.
Note 4: ADCCLK = SYSCLK/16. This is following an initial startup time of approximately 80µs.
Note 5: Base line accuracy of reference source + 0.25% introduced by the MAX31782.
Note 6: The voltage applied to the pins must not exceed their corresponding absolute maximum voltages.
Note 7: ADC has no missing codes.
Note 8: Minimum SCL frequency applies only when in I
2
C master mode.
Note 9: After this period, the first clock pulse can be generated.
Note 10: This device internally provides a hold time of at least 25ns for the SDA signal (referenced to the V
IHMIN
of the SCL signal)
to bridge the undefined region of the falling edge of SCL.
Note 11: C
B
—Total capacitance of one bus line in pF.
Note 12: Filters on SDA and SCL suppress noise spikes at the input buffers and delay the sampling instant.
Figure 1. I
2
C-Compatible Bus Timing Diagram
SCL
NOTE: TIMING IS REFERENCED TO V
ILMAX
AND V
IHMIN
.
SDA
STOP START REPEATED
START
t
BUF
t
HD:STA
t
HD:DAT
t
SU:DAT
t
SU:STO
t
HD:STA
t
SP
t
SU:STA
t
HIGH
t
R
t
F
t
LOW
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
JTAG Logic Reference V
REF
V
DD
/2 V
TCK High Time t
TH
1
Fs
TCK Low Time t
TL
1
Fs
TCK Low to TDO Output t
TLQ
0.125
Fs
TMS, TDI Input Setup to TCK
High
t
DVTH
0.30
Fs
TMS, TDI Input Hold after TCK
High
t
THDX
0.25
Fs