Datasheet
Maxim Integrated
│
9
MAX31865 Evaluation Kit Evaluates: MAX31865
www.maximintegrated.com
Figure 4. MAX31865 EV Kit Schematic (Sheet 1 of 2)
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1
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EP
21
U1
MAX31865 - DUT
FORCE+
FORCE2
RTDIN+
RTDIN-
FORCE-
GND2
GND
SDO
GND1
NC
GND
C4
DNP
C2
0.1uF
GND
3V3 TP1
3.3V
C5
0.1uF
GND
R6 0
R7 0
R8 0
R9 0
R100
TP2
DRDY
R4
1.2k
D1
RedLED
3V3
TP3
SDO
TP4
CS
TP5
SCLK
TP6
SDI
TP9
GND
TP7
GND
R34k
R1DNP
R2DNP
Reference Resistor (RREF)
FORCE+
FORCE2
RTDIN+
RTDIN-
FORCE-
RTD Interface (2,3,4-Wire Selectable)
IFORCE+
IFORCE-
VSENSE-
VSENSE+
C10
0.1uF
--------> RTD <-------
PCB Layout Notes:
1. Place MAX31865 close to RTD terminal strip to minimize errors due to trace resistance
2. Use thick traces (more copper) for all 4 traces to RTD terminal strip
3. Balance trace lengths for all 4 traces to RTD terminal strip
4. Decoupling cap close to pin
SD0_MASTER
CS#_MASTER
SCLK_MASTER
SDI_MASTER
DRDY#_MASTER
To SPI Master
Reference Resistor Note:
Populate one RRef Footprint
(0805,1206, through Hole) footprints
available.
Use a high accuracy low drift
component
MOSI
MISO
GND
VDD
DVDD
RTD Interface Notes:
For 2-wire configuration use an external wire to short IFORCE+ to VSENSE+ at the
terminal strip
For 2- and 3-wire configuration use an external wire to short VSENSE- to IFORCE-
at the terminal strip
DGND
CS#
SCLK
SDI
BIAS
REFIN+
REFIN-
ISENSOR
DRDY#
3.3V_MASTER
R5 0
2
3
4
1
RTD Connect
CON4
R11
10M
RTDIN+