Datasheet

ManualsBrandsMAXIM INTEGRATED ManualsLinear ICsLinear IC - Custom amplification Limiting amplifier TQFN 20

General Description

The MAX3272/MAX3272A 2.5Gbps limiting amplifiers

accept a wide range of input voltages and provide a

constant-level output voltage with controlled edge

speeds. Additional features include power detectors

with programmable loss-of-signal (LOS) indication, an

optional squelch function that mutes the data output sig-

nal when the input voltage falls below a programmable

threshold, and an output polarity selector. These parts

exhibit excellent jitter performance and have low power

dissipation.

The MAX3272/MAX3272A feature current-mode logic

(CML) data outputs that are tolerant of inductive con-

nectors, and are available in a 4mm ✕ 4mm QFN pack-

age or in die form (MAX3272 only). Along with the

MAX3271, the MAX3272/MAX3272A are ideal for low-

power, compact optical receivers.

Applications

Gigabit Ethernet Optical Receivers

Fibre Channel Optical Receivers

System Interconnects

2.5Gbps Optical Receivers

SONET/SDH Receivers

Features

♦ Single +3.3V Power Supply

♦ 33mA Supply Current

♦ 5ps Deterministic Jitter

♦ 90ps Edge Speed

♦ Output Squelch Function

♦ Programmable Loss-of-Signal Function

♦ CML Output Interface

♦ 20-Pin 4mm ✕ 4mm QFN or Thin QFN Package

♦ Selectable Output Polarity

MAX3272/MAX3272A

+3.3V, 2.5Gbps Low-Power

Limiting Amplifiers

________________________________________________________________ Maxim Integrated Products 1

Ordering Information

+3.3V

CAZ1

OUTPOL

CAZ2 V

0.1µF

TH SQUELCH

CLOS

100Ω

IN-

IN+

OUT+

SDI+ SDO+

SDO-

SCLKO-

SCLKO+

SDI-

GND

CDR

OUT-

MAX3271

MAX3272/

MAX3272A

MAX3873

LOSGND

LOSS

SIGNAL

LOS

LEVEL

Typical Operating Circuit

19-2269; Rev 3; 11/04

For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at

1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.

Pin Configuration appears at end of data sheet.

Typical Operating Circuits continue at end of data sheet.

PART

TEMP RANGE

PIN-

PACKAGE

CODE

MAX3272EGP

-40°C to +85°C

20 QFN G2044-3

MAX3272E/D

-40°C to +85°C

Dice* —

MAX3272AETP+

-40°C to +85°C 20 Thin QFN

T2044-3

MAX3272AEGP

-40°C to +85°C

20 QFN G2044-3

+ Denotes Lead-Free Package.

*Dice are designed and guaranteed to operate from -40°C to

+85°C, but are tested only at T

= +25°C.

EVALUATION KIT

AVAILABLE

Summary of content (14 pages)

PAGE 1
9-2269; Rev 3; 11/04 KIT ATION EVALU E L B A AVAIL +3.3V, 2.5Gbps Low-Power Limiting Amplifiers Features The MAX3272/MAX3272A 2.5Gbps limiting amplifiers accept a wide range of input voltages and provide a constant-level output voltage with controlled edge speeds.
PAGE 2
MAX3272/MAX3272A +3.3V, 2.5Gbps Low-Power Limiting Amplifiers ABSOLUTE MAXIMUM RATINGS Continuous Current at CML Outputs (OUT+, OUT-) .........................-25mA to +25mA Continuous Power Dissipation at +85°C 20-Pin Thin QFN (derate 16.9mW/°C above +85°C) ......1.1W 20-Pin QFN (derate 20mW/°C above +85°C) .................1.3W Storage Ambient Temperature Range (TSTG) .................................................-55°C to +150°C Operating Junction Temperature Range (TJ) ...............................
PAGE 3
+3.3V, 2.5Gbps Low-Power Limiting Amplifiers (VCC = +3.0V to +3.6V, TA = -40°C to +85°C. Typical values are at VCC = +3.3V and TA = +25°C, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS High LOS Deassert Level RTH = 80Ω (Notes 3, 10) LOS Output High Voltage Sinking 30µA LOS Output Low Voltage Sourcing 1.2mA MIN TYP MAX UNITS 73 124.7 mVP-P 2.4 V Squelch Input Current 0.4 V 400 µA Dice are designed and guaranteed from -40°C to +85°C but are tested only at TA = +25°C.
PAGE 4
Typical Operating Characteristics (continued) (VCC = +3.3V, TA = +25°C, unless otherwise noted.) LOS HYSTERESIS vs. AMBIENT TEMPERATURE 7 4.5 HYSTERESIS (dB) 6 5 4 3 2 VIN 4.0 RTH = 80Ω VOUT 3.5 3.0 RTH = 20kΩ VLOS RTH = 1kΩ 2.5 1 CCLOS = 0.01µF 2.0 0 10 100 1000 10,000 10 35 60 AMBIENT TEMPERATURE (°C) LOSS OF SIGNAL TRESHOLD vs. RTH DATA OUTPUT EYE DIAGRAM (MINIMUM INPUT) XXXXXXXX 50 45 85 20µs/div DATA OUTPUT EYE DIAGRAM (MAXIMUM INPUT) 2.
PAGE 5
+3.3V, 2.5Gbps Low-Power Limiting Amplifiers COMMON-MODE REJECTION RATIO vs. FREQUENCY 18.5 MAX3272 toc14 12 MAX3272 toc13 10 18.0 DEASSERT 8 17.5 VIN (mVP-P) COMMON-MODE REJECTION RATIO (dB) 19.0 LOS ASSERT AND DEASSERT LEVELS vs. DATA RATE 17.0 16.5 6 ASSERT 4 16.0 223 - 1 PRBS PATTERN RTH = 20kΩ CIN = 0.1µF 2 15.5 15.
PAGE 6
MAX3272/MAX3272A +3.3V, 2.5Gbps Low-Power Limiting Amplifiers Detailed Description VCC Figure 2 is a functional diagram of the MAX3272/ MAX3272A, comprising a CML input buffer, power detector and loss-of- signal indicators, gain stage, offsetcorrection loop, and CML output buffer. ICC IOUT 50Ω CML Input Buffer 50Ω The input buffer (Figure 3) provides 100Ω input impedance between IN+ and IN-.
PAGE 7
+3.3V, 2.5Gbps Low-Power Limiting Amplifiers VCC VCC 540Ω 540Ω 0.25pF IN+ 8kΩ 110Ω LOS IN0.25pF ESD STRUCTURE ESD STRUCTURES GND Figure 4a. LOS Output Circuit for MAX3272 VCC GND Figure 3. Input Circuit Two control voltages VASSERT, and VDEASSERT, define the LOS assert and deassert levels. To prevent LOS chatter in the region of the programmed threshold, approximately 3.3dB of hysteresis is built into the LOS assert/deassert function.
PAGE 8
MAX3272/MAX3272A +3.3V, 2.5Gbps Low-Power Limiting Amplifiers Design Procedure VCC ESD STRUCTURES 50Ω 50Ω OUT+ Program the LOS Assert Threshold External resistor R TH programs the loss-of-signal threshold. See the LOS Threshold vs. RTH graph in the the Typical Operating Characteristics section to select the appropriate resistor. Select the Coupling Capacitors OUT- GND Select the Offset-Correction Capacitor LEVEL Figure 5.
PAGE 9
+3.3V, 2.5Gbps Low-Power Limiting Amplifiers VCC CAZ1 CAZ2 GND OUTPOL TOP VIEW 20 19 18 17 16 GND 1 15 VCC IN+ 2 14 OUT+ TH 5 VCC 6 7 8 9 13 OUT- 12 VCC 11 LEVEL 10 LOS 4 LOS GND MAX3272/ MAX3272A SQUELCH 3 CLOS IN- QFN* VCC CAZ1 CAZ2 GND OUTPOL NOTE: EXPOSED PAD MUST BE CONNECTED TO SUPPLY GROUND.
PAGE 10
+3.3V, 2.5Gbps Low-Power Limiting Amplifiers MAX3272/MAX3272A Typical Operating Circuit (continued) CAZ +3.3V +3.3V CAZ1 CAZ2 VCC MAX3272 OUTPOL +3.3V VCC OUT+ IN+ SDI+ SDO+ SDO- 0.1µF 100Ω 0.1µF MAX3873 IN- OUT- MAX3271 CLOS TH SQUELCH GND LOS LOS CDR SCLKO+ SCLKOGND SDI- LEVEL +3.
PAGE 11
+3.3V, 2.5Gbps Low-Power Limiting Amplifiers VCC (PAD 21) N.C. (PAD 20) CAZ1 (PAD 19) CAZ2 (PAD 18) GND (PAD 17) OUTPOL (PAD 16) GND (PAD 1) VCC (PAD 15) IN+ (PAD 2) OUT+ (PAD 14) IN(PAD 3) OUT(PAD 13) GND (PAD 4) 62 mils 1.57mm VCC (PAD 12) TH (PAD 5) LEVEL (PAD 11) VCC (PAD 6) CLOS (PAD 7) SQUELCH (PAD 8) LOS (PAD 9) LOS (PAD 10) 66 mils 1.68mm TRANSISTOR COUNT: 726 PROCESS: SiGe Bipolar SUBSTRATE: Insulator, Connect to GND DIE SIZE: 1.68mm ✕ 1.
PAGE 12
Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.) 12,16,20, 24L QFN.EPS MAX3272/MAX3272A +3.3V, 2.5Gbps Low-Power Limiting Amplifiers PACKAGE OUTLINE 12,16,20,24L QFN, 4x4x0.
PAGE 13
+3.3V, 2.5Gbps Low-Power Limiting Amplifiers PACKAGE OUTLINE 12,16,20,24L QFN, 4x4x0.90 MM 21-0106 E 2 2 ______________________________________________________________________________________ 13 MAX3272/MAX3272A Package Information (continued) (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.
PAGE 14
Package Information (continued) (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.) 24L QFN THIN.EPS MAX3272/MAX3272A +3.3V, 2.5Gbps Low-Power Limiting Amplifiers PACKAGE OUTLINE 12, 16, 20, 24L THIN QFN, 4x4x0.8mm 21-0139 C 1 2 PACKAGE OUTLINE 12, 16, 20, 24L THIN QFN, 4x4x0.