Datasheet

MAX3372E–MAX3379E/MAX3390E–MAX3393E
±15kV ESD-Protected, 1µA, 16Mbps, Dual/Quad
Low-Voltage Level Translators in UCSP
5
Maxim Integrated
Note 1: All units are 100% production tested at T
A
= +25°C. Limits over the operating temperature range are guaranteed by design
and not production tested.
Note 2: For normal operation, ensure V
L
< (V
CC
+ 0.3V). During power-up, V
L
> (V
CC
+ 0.3V) will not damage the device.
Note 3: To ensure maximum ESD protection, place a 1µF capacitor between V
CC
and GND. See Applications Circuits .
Note 4: 10% to 90%
Note 5: 90% to 10%
TIMING CHARACTERISTICS (continued)
(V
CC
= +1.65V to +5.5V, V
L
= +1.2V to (V
CC
+ 0.3V), GND = 0, R
LOAD
= 1MΩ, I/O test signal of Figure 1, T
A
= T
MIN
to T
MAX
, unless
otherwise noted. Typical values are at V
CC
= +3.3V, V
L
= +1.8V, T
A
= +25°C, unless otherwise noted.) (Notes 1, 2)
PARAMETER SYM B O L CONDITIONS MIN TYP MAX UNITS
+1.2V ≤ V
L
≤ V
CC
≤ +3.3V
I/O V
CC
_ Rise Time (Note 4) t
RVCC
25 ns
I/O V
CC
_ Fall Time (Note 5) t
FVCC
30 ns
I/O V
L
_ Rise Time (Note 4) t
RVL
30 ns
I/O V
L
_ Fall Time (Note 5) t
FVL
30 ns
I/O
VL-VCC
Driving I/O V
L
_20
Propagation Delay
I/O
VCC-VL
Driving I/O V
CC
_20
ns
Channel-to-Channel Skew t
SKEW
Each translator equally loaded
10 ns
Maximum Data Rate
10 Mbps
+2.5V ≤ V
L
≤ V
CC
≤ +3.3V
I/O V
CC
_ Rise Time (Note 4) t
RVCC
15 ns
I/O V
CC
_ Fall Time (Note 5) t
FVCC
15 ns
I/O V
L
_ Rise Time (Note 4) t
RVL
15 ns
I/O V
L
_ Fall Time (Note 5) t
FVL
15 ns
I/O
VL-VCC
Driving I/O V
L
_15
Propagation Delay
I/O
VCC-VL
Driving I/O V
CC
_15
ns
Channel-to-Channel Skew t
SKEW
Each translator equally loaded 10 ns
Maximum Data Rate 16 Mbps
+1.8V ≤ V
L
≤ V
CC
≤ +2.5V
I/O V
CC
_ Rise Time (Note 4) t
RVCC
15 ns
I/O V
CC
_ Fall Time (Note 5) t
FVCC
15 ns
I/O V
L
_ Rise Time (Note 4) t
RVL
15 ns
I/O V
L
_ Fall Time (Note 5) t
FVL
15 ns
I/O
VL-VCC
Driving I/O V
L
_15
Propagation Delay
I/O
VCC-VL
Driving I/O V
CC
_15
ns
Channel-to-Channel Skew t
SKEW
Each translator equally loaded 10 ns
Maximum Data Rate 16 Mbps