Datasheet

MAX3394E/MAX3395E/MAX3396E
±15kV ESD-Protected, High-Drive Current, Dual-/Quad-/
Octal-Level Translators with Speed-Up Circuitry
12 ______________________________________________________________________________________
GND GND GND
+1.8V
SYSTEM
CONTROLLER
+3.3V
SYSTEM
V
L
V
CC
I/O V
L
1
I/O V
L
2
I/O V
CC
1
I/O V
CC
2
CLK
DATA
CLK
DATA
+3.3V+1.8V
EN
EN
0.1μF
1μF
0.1μF
MAX3394E
Typical Operating Circuit
M
P2
M
P1
M
N4
M
N3
GATE CONTROL
SLEW-RATE
ENHANCEMENT
N-CHANNEL
PASS-FET
I/O V
L_
I/O V
CC_
V
L
V
CC
V
L
V
CC
Functional Diagram
itance with a characteristic RC charging waveform.
When the low-to-high transition threshold (V
CC-TH
or V
L-
TH
) is reached, the rise time accelerators switch on,
sourcing 15mA to fully charge the bus capacitance.
External pullup resistors reduce the time needed to
reach the low-to-high transition threshold, thereby
increasing the data rate. In the logic-low state however,
external pullup resistors increase the DC current
through the internal pass-FET, increasing the output
voltage of the device.
Smart-Card Interface
The MAX3395E provides level translation for Class A, B,
and C smart cards. When supply voltage V
CC
is inter-
rupted due to the disconnection of a smart card, the
device does not latch up. Normal operation resumes
upon restoration of the V
CC
supply voltage. The
MAX3395E provides bidirectional level translation on
four I/O lines, making it well suited for buffering and
translating 4-wire serial interfaces.
UCSP Applications Information
For the latest application details on UCSP construction,
dimensions, tape carrier information, PCB techniques,
bump-pad layout, and recommended reflow temperature
profiles, as well as the latest information on reliability test-
ing results, go to Maxim’s web site at www.maxim-
ic.com/ucsp to find the Application Note 1891:
Wafer-Level Packaging (WLP) and Its Applications .