Datasheet

MAX3394E/MAX3395E/MAX3396E
The MAX3394E/MAX3395E/MAX3396E feature a tri-
state output mode, thermal-shutdown protection, and
±15kV Human Body Model (HBM) ESD protection on
the V
CC
side for greater protection in applications that
route signals externally.
The MAX3394E/MAX3395E/MAX3396E accept V
CC
volt-
ages from +1.65V to +5.5V, and V
L
voltages from +1.2V
to V
CC
, making them ideal for data transfer between low-
voltage ASIC/PLDs and higher voltage systems. The
MAX3394E/MAX3395E/MAX3396E operate at a guaran-
teed data rate of 6Mbps with push-pull drivers and
1Mbps with open-drain drivers.
Level Translation
The MAX3394E/MAX3395E/MAX3396E utilize a trans-
mission gate architecture to provide bidirectional level
translation between I/O V
L
_ and I/O V
CC
_. The trans-
mission gate architecture is comprised of a pass-FET,
gate-control logic, and slew-rate enhancement circuit-
ry. When both I/O V
L
_ and I/O V
CC
_ are logic high, the
gate-control logic disables the pass-FET, providing
±15kV ESD-Protected, High-Drive Current, Dual-/Quad-/
Octal-Level Translators with Speed-Up Circuitry
8 _______________________________________________________________________________________
MAX3394E
MAX3395E
MAX3396E
t
FVCC
t
RVCC
t
I/OVL-VCC
I/O V
L_
I/O V
CC_
50Ω
V
L
V
L
V
CC
10%
10%
90%
90%
50%
50%
50%
50%
V
CC
C
IOVCC
t
I/OVL-VCC
V
CC
EN
V
L
I/O V
CC
I/O V
L
Figure 1. Push-Pull Driving I/O V
L_
Test Circuit and Timing
MAX3394E
MAX3395E
MAX3396E
t
FVCC
t
RVCC
t
I/OVL-VCC
I/O V
L_
I/O V
CC_
V
L
V
L
V
CC
10%
10%
90%
90%
50%
50%
50%
50%
V
CC
C
IOVCC
t
I/OVL-VCC
I/O V
CC
V
GATE
V
L
V
CC
EN
V
GATE
Figure 2. Open-Drain Driving I/O V
L_
Test Circuit and Timing