Datasheet

ManualsBrandsMAXIM INTEGRATED ManualsLinear ICsMAX3420EECJ+

AVAILABLE

EVALUATION KIT AVAILABLE

Functional Diagrams

Pin Configurations appear at end of data sheet.

Functional Diagrams continued at end of data sheet.

UCSP is a trademark of Maxim Integrated Products, Inc.

For pricing, delivery, and

ordering information, please contact Maxim Direct

at 1-888-629-4642, or visit Maxim’s website at www.maximintegrated.com.

General Description

The MAX3420E contains the digital logic and analog

circuitry necessary to implement a full-speed USB

peripheral compliant to USB specification rev 2.0. A

built-in full-speed transceiver features ±15kV ESD pro-

tection and programmable USB connect and discon-

nect. An internal serial-interface engine (SIE) handles

low-level USB protocol details such as error checking

and bus retries. The MAX3420E operates using a regis-

ter set accessed by an SPI™ interface that operates up

to 26MHz. Any SPI master (microprocessor, ASIC, DSP,

etc.) can add USB functionality using the simple 3- or

4-wire SPI interface.

Internal level translators allow the SPI interface to run at

a system voltage between 1.71V and 3.6V. USB timed

operations are done inside the MAX3420E with inter-

rupts provided at completion so an SPI master does not

need timers to meet USB timing requirements. The

MAX3420E includes four general-purpose inputs and

outputs so any microprocessor that uses I/O pins to

implement the SPI interface can reclaim the I/O pins

and gain additional ones.

The MAX3420E operates over the extended -40°C to

+85°C temperature range and is available in a 32-pin

LQFP package (7mm x 7mm) and a space-saving 24-

pin TQFN package (4mm x 4mm).

Applications

Features

♦ Microprocessor-Independent USB Solution

♦ Complies with USB Specification Revision 2.0

(Full-Speed Operation)

♦ Integrated Full-Speed USB Transceiver

♦ Firmware/Hardware Control of an Internal D+

Pullup Resistor

♦ Programmable 3- or 4-Wire 26MHz SPI Interface

♦ Level Translators and V

Input Allow Independent

System Interface Voltage

♦ Internal Comparator Detects V

BUS

for

Self-Powered Applications

♦ ESD Protection on D+, D-, and VBCOMP

♦ Interrupt Output Pin (Level or Programmable

Edge) Allows Polled or Interrupt-Driven SPI

Interface

♦ Intelligent USB Serial-Interface Engine (SIE)

Automatically Handles USB Flow Control and

Double Buffering

Handles Low-Level USB Signaling Details

Contains Timers for USB Time-Sensitive

Operations So SPI Master Does Not Need to

Time Events

♦ Built-In Endpoint FIFOs

EP0: CONTROL (64 Bytes)

EP1: OUT, Bulk or Interrupt, 2 x 64 Bytes

(Double-Buffered)

EP2: IN, Bulk or Interrupt, 2 x 64 Bytes

(Double-Buffered)

EP3: IN, Bulk or Interrupt (64 Bytes)

♦ Double-Buffered Data Endpoints Increase

Throughput by Allowing the SPI Master to

Transfer Data Concurrently with USB Transfers

Over the Same Endpoint

♦ SETUP Data Has Its Own 8-Byte FIFO, Simplifying

Firmware

♦ Four General-Purpose Inputs and Four General-

Purpose Outputs

♦ Space-Saving LQFP and TQFN Packages

USB Peripheral Controller

with SPI Interface

19-3781; Rev 3; 12/10

Cell Phones

PC Peripherals

Microprocessors and

DSPs

Custom USB Devices

Cameras

Desktop Routers

PLCs

Set-Top Boxes

PDAs

MP3 Players

Instrumentation

PART TEMP RANGE PIN-PACKAGE

MAX3420EETG+ -40°C to +85°C 24 TQFN-EP*

MAX3420EECJ+ -40°C to +85°C 32 LQFP

MAX3420EECJ/V+ -40°C to +85°C 32 LQFP

Ordering Information

+Denotes a lead(Pb)-free/RoHS-compliant package.

EP = Exposed pad.

/V denotes an automotive qualified part.

SPI is a trademark of Motorola, Inc.

MAX3420E

Summary of content (22 pages)

PAGE 1
EVALUATION KIT AVAILABLE MAX3420E LE AVAILAB USB Peripheral Controller with SPI Interface General Description Features The MAX3420E contains the digital logic and analog circuitry necessary to implement a full-speed USB peripheral compliant to USB specification rev 2.0. A built-in full-speed transceiver features ±15kV ESD protection and programmable USB connect and disconnect. An internal serial-interface engine (SIE) handles low-level USB protocol details such as error checking and bus retries.
PAGE 2
MAX3420E USB Peripheral Controller with SPI Interface Typical Application Circuits 3.3V REGULATOR SPI 3, 4 USB MAX3420E INT μP The MAX3420E connects to any microprocessor using 3 or 4 interface pins (Figure 1). On a simple microprocessor without SPI hardware, these can be bitbanged general-purpose I/O pins. Four GPIN and four GPOUT pins on the MAX3420E more than replace the µP pins necessary to implement the interface.
PAGE 3
MAX3420E USB Peripheral Controller with SPI Interface Functional Diagram VL RES XO XI VCC INTERNAL POR RESET LOGIC OSC AND PLL 4x 1.
PAGE 4
MAX3420E USB Peripheral Controller with SPI Interface Pin Description PIN TQFN-EP LQFP 1 1 NAME INPUT/ OUTPUT Output General-Purpose Push-Pull Outputs. GPOUT3–GPOUT0 logic levels are referenced to the voltage on VL. The SPI master controls the GPOUT3–GPOUT0 states by writing to bit 3 through bit 0 of the IOPINS (R20) register. Level-Translator Reference Voltage. Connect VL to the system’s 1.71V to 3.6V logic-level power supply. Bypass VL to ground with a 0.
PAGE 5
MAX3420E USB Peripheral Controller with SPI Interface Pin Description (continued) PIN TQFN-EP LQFP 17 22, 23 NAME INPUT/ OUTPUT VCC Input USB Transceiver Power-Supply Input. Connect VCC to a positive 3.3V power supply. Bypass VCC to ground with a 1.0μF ceramic capacitor as close to the VCC pin as possible. FUNCTION 18 24 VBCOMP Input VBUS Comparator Input.
PAGE 6
MAX3420E USB Peripheral Controller with SPI Interface The first five registers (R0–R4) access endpoint FIFOs. To access a FIFO, an initial command byte sets the register address and then consecutive reads or writes keep the same register address to access subsequent FIFO bytes. The remaining registers (R5–R20) control the operation of the MAX3420E.
PAGE 7
MAX3420E USB Peripheral Controller with SPI Interface GPIN1 22 GPIN2 23 *EP GPIN3 24 + TQFN *CONNECT EXPOSED PAD TO GND. Maxim Integrated 5 6 GPOUT3 GND 4 GPOUT2 3 VL 2 GPOUT1 GPOUT0 1 D- GND GND INT 17 16 N.C. 26 15 GPX 27 14 MOSI N.C. 28 13 MISO 12 SS N.C. 25 12 GPX XI 11 MOSI XO 10 MISO 9 SS GPIN0 29 8 SCLK GPIN1 30 11 SCLK 7 RES GPIN2 31 10 RES GPIN3 32 9 N.C.
PAGE 8
MAX3420E USB Peripheral Controller with SPI Interface ABSOLUTE MAXIMUM RATINGS (All voltages referenced to GND, unless otherwise noted.) VCC ......................................................................... -0.3V to +4V VL .............................................................................-0.3V to +4V VBCOMP .................................................................-0.3V to +6V D+, D-, XI, XO ............................................-0.3V to (VCC + 0.
PAGE 9
MAX3420E USB Peripheral Controller with SPI Interface ELECTRICAL CHARACTERISTICS (continued) (VCC = +3V to +3.6V, VL = +1.71V to +3.6V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at VCC = +3.3V, VL = +2.5V, TA = +25°C.) (Note 1) PARAMETER SYMBOL Single-Ended Receiver Input Low Voltage VIL Single-Ended Receiver Input High Voltage VIH CONDITIONS MIN TYP MAX UNITS 0.8 V 2.0 Single-Ended Receiver Hysteresis Voltage V 0.
PAGE 10
MAX3420E USB Peripheral Controller with SPI Interface TIMING CHARACTERISTICS (VCC = +3V to +3.6V, VL = +1.71V to +3.6V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at VCC = +3.3V, VL = +2.5V, TA = +25°C.
PAGE 11
MAX3420E USB Peripheral Controller with SPI Interface Test Circuits and Timing Diagrams TEST POINT tFALL tRISE MAX3420E 33Ω D+ OR D- VOH 90% CL 15kΩ 10% VOL Figure 7. Load for D+/D- AC Measurements Figure 6. Rise and Fall Times tL SS tCSS tCSW tCH tCL 2 1 8 10 9 tT 16 SCLK tDS tCP MOSI tDH MISO tDO HIGH IMPEDANCE HIGH IMPEDANCE Figure 8.
PAGE 12
MAX3420E USB Peripheral Controller with SPI Interface Typical Operating Characteristics (VCC = +3.3V, VL = +3.3V, TA = +25°C.) MAX3420E toc01 EYE DIAGRAM 4 D+ AND D- (V) 3 2 1 0 -1 0 10 20 30 40 50 60 70 80 TIME (ns) Detailed Description The MAX3420E contains the digital logic and analog circuitry necessary to implement a full-speed USB peripheral that complies with the USB specification rev 2.0. ESD protection of ±15kV is provided on D+, D-, and VBCOMP.
PAGE 13
MAX3420E USB Peripheral Controller with SPI Interface Table 2. Internal Pullup Resistor Control CONNECT VBGATE VBUS_DET PULLUP 0 X X Not Connected 1 0 X Connected 1 1 0 Not Connected 1 1 1 Connected (NOVBUSIRQ)) and disconnect the internal 1.5kΩ pullup resistor. If the device using the MAX3420E is bus powered (through a +3.3V regulator connected to VCC), the MAX3420E VBCOMP input can be used as a general-purpose input.
PAGE 14
MAX3420E USB Peripheral Controller with SPI Interface pending (Figure 10). Set the POSINT bit in the PINCTL (R17) register to make INT active high, and clear the POSINT bit to make INT active low. GPOUT WRITE GPOUT PIN REGISTER BIT GPIN3–GPIN0, GPOUT3–GPOUT0 and GPX The MAX3420E has four general-purpose inputs (GPIN3–GPIN0), four general-purpose outputs (GPOUT3–GPOUT0), and a multiplexed output pin (GPX). GPIN3 through GPIN0 all have weak internal pullup resistors to VL.
PAGE 15
MAX3420E USB Peripheral Controller with SPI Interface SS MISO SPI MODE 0,0 OR 1,1 Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 D1 D0 * SCLK MODE 0,0 SCLK MODE 1,1 MOSI D7 D6 D5 D4 D3 D2 * *MSB OF NEXT BYTE IN BURST MODE (SS REMAINS LOW) Figure 14. SPI Clocking Modes In full-duplex mode (FDUPSPI = 1), the MOSI and MISO pins are separate, and the MISO pin drives only when SS is low.
PAGE 16
MAX3420E USB Peripheral Controller with SPI Interface SPI Half- and Full-Duplex Operation The MAX3420E can be programmed to operate in halfduplex (a bidirectional data pin) or full-duplex (one data-in and one data-out pin) mode. The SPI master sets a register bit called FDUPSPI (full-duplex SPI) to 1 for full-duplex, and 0 for half-duplex operation. Halfduplex is the power-on default.
PAGE 17
MAX3420E USB Peripheral Controller with SPI Interface SS MISO SPI MODE 0,0 (CPOL = 0, CPHA = 0) SUSPIRQ URESIRQ REG4 REG3 SUDAVIRQ IN3BAVIRQ IN2BAVIRQ OUT1DAVIRQ OUT0DAVIRQ IN0BAVIRQ X SCLK MOSI REG2 REG1 REG0 0 DIR ACKSTAT Figure 15. SPI Port in Full-Duplex Mode (5) To write SPI data, the SPI master keeps its output driver on and clocks subsequent bytes into the MOSI pin.
PAGE 18
MAX3420E USB Peripheral Controller with SPI Interface preshutdown tasks before it requests the MAX3420E to enter the power-down state by setting PWRDOWN = 1. Wakeup and USB Resume The MAX3420E may wake up in three ways while it is in the power-down state: (1) The SPI master clears the PWRDOWN bit in the USBCTL (R15) register (this is also achieved by a chip reset). (2) The SPI master signals a USB remote wakeup by setting the SIGRWU bit in the USBCTL (R15) register.
PAGE 19
MAX3420E USB Peripheral Controller with SPI Interface 3.3V REGULATOR MAX6349TL 12MHz 1.0μF CERAMIC 0.1μF CXI CXO 10kΩ 4.7μF VCC VBUS XI XO INT MOSI MISO SCLK SS 33Ω D+ USB "B" CONNECTOR VL RES D+ 33Ω D- MAX3420E D- μP GND VBCOMP GPI GND GPIN GPOUT 4 4 Figure 16. MAX3420E in a Bus-Powered Application MAX3420E in a Bus-Powered Application Figure 16 depicts the MAX3420E in a peripheral device that is powered by VBUS.
PAGE 20
MAX3420E USB Peripheral Controller with SPI Interface +3.3V 12MHz 1.0μF CERAMIC VCC CXI VL CXO XI XO RES VBUS GPX INT MOSI MISO SCLK SS 33Ω D+ USB "B" CONNECTOR 0.1μF D+ 33Ω D- MAX3420E D- GND N.C. μP N.C. VBCOMP 1.0μF CERAMIC GND GPIN GPOUT 4 4 GPIO Figure 17. MAX3420E in a Self-Powered Application The V BUS detect input, VBCOMP, is an important MAX3420E feature. Because the µP is powered whether the USB device is plugged in or not, it needs some way to detect a plug-in event.
PAGE 21
MAX3420E USB Peripheral Controller with SPI Interface RC 1MΩ CHARGE-CURRENTLIMIT RESISTOR HIGHVOLTAGE DC SOURCE Cs 100pF possible. D+, D-, and VBCOMP provide protection to the following limits: RD 1.5kΩ • ±15kV using the Human Body Model • ±8kV using the Contact Discharge method specified in IEC 61000-4-2 DISCHARGE RESISTANCE DEVICE UNDER TEST STORAGE CAPACITOR • ±12kV using the IEC 61000-4-2 Air Gap Method ESD Test Conditions ESD performance depends on a variety of conditions.
PAGE 22
MAX3420E USB Peripheral Controller with SPI Interface Revision History REVISION NUMBER REVISION DATE 2 6/07 3 12/10 DESCRIPTION PAGES CHANGED 4, 5, 19, 20, 22, 23, 24, 25 Various changes Added the MAX3420EECJ/V+ part number to the Ordering Information 1 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied.