Datasheet

ManualsBrandsMAXIM INTEGRATED ManualsClock & Timing ICsTQFN 48

General Description

The MAX3634 burst-mode clock phase aligner (CPA) is

designed specifically for 622Mbps or 1244Mbps GPON

(ITU G.984) optical line terminal (OLT) receiver applica-

tions. The MAX3634 provides clock and clock-aligned

resynchronized upstream data through differential

LVPECL outputs. Using the OLT system clock as a ref-

erence, the MAX3634 aligns to the input data and

acquires within the first 13 bits of the burst. The CPA

operates with received data that is frequency locked to

the OLT reference. The acquisition time, bit-error ratio,

and jitter tolerance all support GPON PMD specifica-

tions. LVPECL high-speed clock and data outputs pro-

vide compatibility with FPGAs at 622Mbps and with the

MAX3885 deserializer at 1244Mbps.

The MAX3634 is available in a low-profile, 7mm x 7mm,

48-lead TQFN package. The MAX3634 operates from a

single +3.3V supply, over the -40°C to +85°C tempera-

ture range.

Applications

622Mbps GPON OLT Receivers

1244Mbps GPON OLT Receivers

Features

♦ DC-Coupled Clock Phase Aligner for Burst-Mode

GPON Applications

♦ 13-Bit Burst Acquisition Time

♦ 0.85UI High-Frequency Jitter Tolerance

♦ Continuous Clock Output

♦ Byte Rate (1/8th Data Rate) Reference Clock Input

♦ Lock Detect Output

♦ LVPECL Serial Data Input and Output

♦ LVPECL Reset Input

MAX3634

622Mbps/1244Mbps Burst-Mode Clock

Phase Aligner for GPON OLT Applications

________________________________________________________________ Maxim Integrated Products 1

Ordering Information

19-3818; Rev 0; 9/05

For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at

1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.

EVALUATION KIT

AVAILABLE

PART

TEMP RANGE

PIN-

PACKAGE

PKG

CODE

MAX3634ETM

-40°C to +85°C

48 TQFN

(7mm x 7mm)

T4877-6

MAX3634

MAX3738

BURST-MODE

TIA/LA

MAX3656

BURST-MODE

LASER DRIVER

MAX3864

MAX3748A

TIA/LA

MAX3872

SONET

CDR

MAX3892

DATA

SERIALIZER

DATA

CLOCK

OLT CLOCK

DATA

BURST RESET

RATESEL

DIVIDE BY 16

DIVIDE BY 8

CONTINUOUS

LASER DRIVER

GPON OPTICAL LINE TERMINATION GPON OPTICAL NETWORK TERMINATION

DATA

BURST ENABLE

CLOCK

UPSTREAM

1244Mbps

DOWNSTREAM

2488Mbps

BURST-MODE

CLOCK PHASE

ALIGNER

Typical Application Circuit

Pin Configuration appears at end of data sheet.

Summary of content (8 pages)

PAGE 1
9-3818; Rev 0; 9/05 KIT ATION EVALU E L B AVAILA 622Mbps/1244Mbps Burst-Mode Clock Phase Aligner for GPON OLT Applications The MAX3634 burst-mode clock phase aligner (CPA) is designed specifically for 622Mbps or 1244Mbps GPON (ITU G.984) optical line terminal (OLT) receiver applications. The MAX3634 provides clock and clock-aligned resynchronized upstream data through differential LVPECL outputs.
PAGE 2
MAX3634 622Mbps/1244Mbps Burst-Mode Clock Phase Aligner for GPON OLT Applications ABSOLUTE MAXIMUM RATINGS VCC, VCCI, VCCO, VCCV ........................................-0.5V to +4.0V SDI±, RST±, REFCLK±, RATESEL, FILT, TEST.............................-0.5V to (VCC + 0.5V) LVPECL Output Current (SDO±, SCLK±, LOCK±).............50mA Continuous Power Dissipation (TA = +85°C) 48-Lead TQFN package (derate 27.8mW/°C above +85°C) .............................1800mW Storage Temperature Range ...................
PAGE 3
622Mbps/1244Mbps Burst-Mode Clock Phase Aligner for GPON OLT Applications (VCC = +3.0V to +3.6V, TA = -40°C to +85°C. Typical values are at VCC = +3.3V, TA = +25°C, unless otherwise noted.
PAGE 4
Typical Operating Characteristics (continued) (VCC = +3.3V and TA = +25°C, unless otherwise noted) JITTER TOLERANCE vs. SDI-TO-REFCLK PHASE (1.244Gbps) JITTER TOLERANCE vs. SDI-TO-REFCLK PHASE (622Mbps) 0.7 LIMITED BY TEST EQUIPMENT 0.6 0.5 0.4 0.3 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.1 0 0 200 0 400 600 800 LIMITED BY TEST EQUIPMENT MAX3634 toc06 0.8 0.2 340 320 SUPPLY CURRENT (mA) 0.8 0.9 JITTER TOLERANCE (UIP-P) 0.9 SUPPLY CURRENT vs. TEMPERATURE MAX3634 toc05 1.0 MAX3634 toc04 1.
PAGE 5
622Mbps/1244Mbps Burst-Mode Clock Phase Aligner for GPON OLT Applications Theory of Operation The MAX3634 CPA provides serial clock and data outputs for GPON upstream bursts. The burst-mode CPA operates on the principle that the recovered clock from the ONT CDR is used at each ONT to clock upstream data bursts out of the ONT controller.
PAGE 6
MAX3634 622Mbps/1244Mbps Burst-Mode Clock Phase Aligner for GPON OLT Applications Input Stage rest (BRST) signal. It then uses the next 8 bits of preamble (10101010) to measure the phase relationship between the reference clock and upstream data (after the internal logic has been reset), and 3 to 5 bits later begins outputting data. The time interval from BRST to the end of the preamble must be no less than 18 bits long.
PAGE 7
622Mbps/1244Mbps Burst-Mode Clock Phase Aligner for GPON OLT Applications TRANSISTOR COUNT: 10,805 PROCESS: Silicon Germanium BiCMOS GND VCCO LOCK- LOCK+ VCCO SDO- SDO+ VCCO SCLK- SCLK+ VCCO GND Chip Information 36 35 34 33 32 31 30 29 28 27 26 25 GND 37 24 VCCO VCC 38 23 TEST10 VCC 39 22 TEST9 RATESEL 40 21 VCCO VCCV 41 20 TEST8 FILT 42 19 TEST7 MAX3634 VCCV 43 18 TEST6 VCC 44 17 TEST5 REFCLK- 45 16 TEST4 15 TEST3 REFCLK+ 46 EP* VCC 47 14 TEST2 13 TEST1 SDI+ SDI- 8 9
PAGE 8
Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.) E DETAIL A 32, 44, 48L QFN.EPS MAX3634 622Mbps/1244Mbps Burst-Mode Clock Phase Aligner for GPON OLT Applications (NE-1) X e E/2 k e D/2 C L (ND-1) X e D D2 D2/2 b L E2/2 C L k E2 C L C L L L e A1 A2 e A PACKAGE OUTLINE 32, 44, 48, 56L THIN QFN, 7x7x0.