Datasheet

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_________________General Description

The MAX3680/MAX3680A deserializer is ideal for con-

verting 622Mbps serial data to 8-bit-wide, 77Mbps par-

allel data in ATM and SDH/SONET applications.

Operating from a single +3.3V supply, this device

accepts PECL serial clock and data inputs, and deliv-

ers TTL clock and data outputs. The MAX3680 also pro-

vides a TTL synchronization input that enables data

realignment and reframing.

The MAX3680/MAX3680A is available in the extended-

industrial temperature range (-40°C to +85°C), in a 28-

pin SSOP package.

__________________________Applications

622Mbps SDH/SONET Transmission Systems

622Mbps ATM/SONET Access Nodes

Add/Drop Multiplexers

Digital Cross-Connects

______________________________Features

♦♦

Single +3.3V Supply

♦♦

622Mbps Serial to 77Mbps Parallel Conversion

♦♦

165mW Power

♦♦

Synchronization Input for Data Realignment and

Reframing (MAX3680)

♦♦

Differential 3.3V PECL Clock and Data Inputs

♦♦

TTL Data Outputs

MAX3680/MAX3680A

+3.3V, 622Mbps, SDH/SONET

1:8 Deserializer with TTL Outputs

________________________________________________________________

Maxim Integrated Products

MAX3675

MAX3664

MAX3680/

MAX3680A

DATA

AND

CLOCK

RECOVERY

OVERHEAD

TERMINATION

LIMITING

AMP

PREAMP

100Ω

PHOTODIODE

= +3.3V

SD+

SD-

THIS SYMBOL REPRESENTS A TRANSMISSION LINE OF CHARACTERISTIC IMPEDANCE Z

= 50Ω.

GND

130Ω 130Ω

82Ω 82Ω

= +3.3V

130Ω 130Ω

82Ω 82Ω

= +3.3V

SCLK+

SCLK-

SYNC

PCLK

PD7

PD6

PD5

PD4

PD3

PD2

PD1

PD0

___________________________________________________________________Typical Operating Circuit

19-1210; Rev 3; 3/07

________________Ordering Information

Pin Configuration appears at end of data sheet.

EVALUATION KIT

AVAILABLE

For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at

1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.

Denotes lead-free package.

PART TEMP RANGE PIN-PACKAGE

MAX3680EAI -40°C to +85°C 28 SSOP

MAX3680EAI+ -40°C to +85°C 28 SSOP

MAX3680AEAI -40°C to +85°C 28 SSOP

Summary of content (8 pages)

PAGE 1
9-1210; Rev 3; 3/07 KIT ATION EVALU E L B AVAILA +3.3V, 622Mbps, SDH/SONET 1:8 Deserializer with TTL Outputs ______________________________Features The MAX3680/MAX3680A deserializer is ideal for converting 622Mbps serial data to 8-bit-wide, 77Mbps parallel data in ATM and SDH/SONET applications. Operating from a single +3.3V supply, this device accepts PECL serial clock and data inputs, and delivers TTL clock and data outputs.
PAGE 2
MAX3680/MAX3680A +3.3V, 622Mbps, SDH/SONET 1:8 Deserializer with TTL Outputs ABSOLUTE MAXIMUM RATINGS Terminal Voltage (with respect to GND) VCC ........................................................................-0.5V to +5V PECL Inputs (SD+/-, SCLK+/-) ................-0.5V to (VCC + 0.5V) TTL Input (SYNC) ....................................-0.5V to (VCC + 0.5V) TTL Outputs (PCLK, PD_)........................-0.5V to (VCC + 0.5V) Continuous Power Dissipation (TA = +85°C) SSOP (derate 9.
PAGE 3
+3.3V, 622Mbps, SDH/SONET 1:8 Deserializer with TTL Outputs SERIAL DATA SETUP TIME vs. TEMPERATURE MAXIMUM SERIAL-CLOCK FREQUENCY vs. TEMPERATURE 1.2 1.1 1.0 0.9 MAX3680-02 MAX3680-01 400 SERIAL DATA-SETUP TIME (ps) 360 320 280 240 200 0.8 -50 -25 0 25 50 75 100 -50 -25 25 50 75 100 SUPPLY CURRENT vs. TEMPERATURE SERIAL DATA HOLD TIME vs. TEMPERATURE 70 MAX3680-03 -100 VCC = +3.
PAGE 4
+3.3V, 622Mbps, SDH/SONET 1:8 Deserializer with TTL Outputs MAX3680/MAX3680A Pin Description PIN NAME FUNCTION MAX3680 MAX3680A 1, 2, 5, 8, 14, 18, 25 1, 2, 5, 8, 14, 18, 25 VCC +3.3V Supply Voltage 3 3 SD+ Noninverting PECL Serial Data Input. Data is clocked on the SCLK signal’s positive transition. 4 4 SD- Inverting PECL Serial Data Input. Data is clocked on the SCLK signal’s positive transition.
PAGE 5
+3.3V, 622Mbps, SDH/SONET 1:8 Deserializer with TTL Outputs MAX3680/MAX3680A SCLK* SD* D1- D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 PCLK PD7 D8- D0 D8 PD6 D7- D1 D9 PD5 D6- D2 D10 PD4 D5- D3 D11 PD3 D4- D4 D12 PD2 D3- D5 D13 PD1 D2- D6 D14 PD0 D1- D7 D15 * SIGNAL SHOWN IS DIFFERENTIAL. FOR EXAMPLE, SCLK = (SCLK+) - (SCLK-). Figure 2a.
PAGE 6
MAX3680/MAX3680A +3.3V, 622Mbps, SDH/SONET 1:8 Deserializer with TTL Outputs SCLK* SD* D1- D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 SYNC PCLK PD7 D8- D1 D9 PD6 D7- D2 D10 PD5 D6- D3 D11 PD4 D5- D4 D12 PD3 D4- D5 D13 PD2 D3- D6 D14 PD1 D2- D7 D15 PD0 D1- D8 D16 * SIGNAL SHOWN IS DIFFERENTIAL. FOR EXAMPLE, SCLK = (SCLK+) - (SCLK-). Figure 2b.
PAGE 7
+3.3V, 622Mbps, SDH/SONET 1:8 Deserializer with TTL Outputs Applications Information THEVENIN-EQUIVALENT TERMINATION +3.3V 130Ω 130Ω MAX3680/ MAX3680A ZO = 50Ω Alternative PECL Input Termination Figure 4 shows alternative PECL input-termination methods. Use Thevenin-equivalent termination when a (VCC - 2V) termination voltage is not available. If AC coupling is necessary, such as when interfacing with an ECL-output device, use the ECL AC-coupling termination.
PAGE 8
________________________________________________________Package Information 2 SSOP.EPS MAX3680/MAX3680A +3.3V, 622Mbps, SDH/SONET 1:8 Deserializer with TTL Outputs 1 INCHES E H MILLIMETERS DIM MIN MAX MIN MAX A 0.068 0.078 1.73 1.99 A1 0.002 0.008 0.05 0.21 B 0.010 0.015 0.25 0.38 C 0.09 0.20 0.004 0.008 SEE VARIATIONS D E e 0.205 0.212 0.0256 BSC 5.20 MILLIMETERS INCHES D D D D D 5.38 MIN MAX MIN MAX 0.239 0.239 0.278 0.249 0.249 0.289 6.07 6.07 7.07 6.33 6.