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General Description

The MAX3873A is a compact, low-power 2.488Gbps/

2.67Gbps clock-recovery and data-retiming IC for

SDH/SONET applications. The phase-locked loop (PLL)

recovers a synchronous clock signal from the serial NRZ

data input. The input data is then retimed by this recov-

ered clock, providing a clean data output. The MAX3873A

meets all SDH/SONET jitter specifications, does not

require an external reference clock to aid in frequency

acquisition, and provides excellent tolerance to both

deterministic and sinusoidal jitter. The MAX3873A pro-

vides a PLL loss-of-lock (LOL) output to indicate whether

the CDR is in lock. The recovered data and clock outputs

are CML with on-chip 50Ω back terminations on each line.

The clock output can be powered down if not used.

The MAX3873A is implemented in Maxim’s second-gener-

ation SiGe process and consumes only 260mW at 3.3V

supply (output clock disabled, low output swing). The

device is available in a 4mm x 4mm 20-pin QFN

exposed-pad package and operates from -40°C to +85°C.

Applications

Switch Matrix Backplanes

SDH/SONET Receivers and Regenerators

Add/Drop Multiplexers

Digital Cross-Connects

SDH/SONET Test Equipment

DWDM Transmission Systems

Features

♦ Fully Integrated Clock Recovery and Data

Retiming

♦ Power Dissipation: 260mW with +3.3V Supply

♦ Clock Jitter Generation: 5mUI

RMS

♦ Exceeds ANSI, ITU, and Bellcore SDH/SONET

Jitter Specifications

♦ Differential Input Range: 50mV

P-P

to 1.6V

P-P

♦ Single +3.3V Power Supply

♦ PLL Fast Track (FASTRACK) Mode Available

♦ Clock Output Can Be Disabled

♦ Input Data Rate: 2.488Gbps or 2.67Gbps

♦ Selectable Output Amplitude

♦ Tolerates 2000 Consecutive Identical Digits

♦ Loss-of-Lock Indicator

♦ Differential CML Data and Clock Outputs

♦ Operating Temperature Range: -40°C to +85°C

MAX3873A

Low-Power, Compact 2.5Gbps/2.7Gbps

Clock-Recovery and Data-Retiming IC

________________________________________________________________

Maxim Integrated Products

19-2577; Rev 2; 5/07

For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,

or visit Maxim’s website at www.maxim-ic.com.

EVALUATION KIT

AVAILABLE

Ordering Information

Typical Application Circuit appears at end of data sheet.

Pin Configuration

PART TEMP RANGE

PIN-

PACKAGE

PKG

CODE

MAX3873AEGP -40°C to +85°C

20 QFN

(4mm x 4mm)

G2044-3

M AX 3873AE TP + -40°C to +85°C

20 TQFN

(4mm x 4mm)

T2044-3

GND

FIL+

FIL-

GND

LOL

FASTRACK

VCC_VCO

MODE

SCLKEN

**NOTE: THE EXPOSED PAD MUST BE

SOLDERED TO THE SUPPLY GROUND.

SCLKO-

SCLKO+

VCC_BUF

SDO-

SDO+

SDI-

SDI+

RATESET

MAX3873A

QFN/TQFN**

TOP VIEW

Denotes lead-free package.

Summary of content (10 pages)

PAGE 1
9-2577; Rev 2; 5/07 KIT ATION EVALU LE B A IL A AV Low-Power, Compact 2.5Gbps/2.7Gbps Clock-Recovery and Data-Retiming IC The MAX3873A is a compact, low-power 2.488Gbps/ 2.67Gbps clock-recovery and data-retiming IC for SDH/SONET applications. The phase-locked loop (PLL) recovers a synchronous clock signal from the serial NRZ data input. The input data is then retimed by this recovered clock, providing a clean data output.
PAGE 2
MAX3873A Low-Power, Compact 2.5Gbps or 2.7Gbps Clock-Recovery and Data-Retiming IC ABSOLUTE MAXIMUM RATINGS Supply Voltage, VCC..............................................-0.5V to +5.0V Voltage at SDI± .............................. (VCC - 1.0V) to (VCC + 0.5V) CML Output Current at SDO±, SCLKO± ............................22mA Voltage at LOL, FASTRACK, FIL±, SCLKEN MODE, RATESET...................................-0.5V to (VCC + 0.5V) Continuous Power Dissipation (TA = +85°C) 20-Lead QFN (derate 20.
PAGE 3
Low-Power, Compact 2.5Gbps or 2.7Gbps Clock-Recovery and Data-Retiming IC (VCC = 3.0V to 3.6V, CF = 0.022µF, TA = -40°C to +85°C. Typical values are at VCC = 3.3V, 2.488Gbps, TA = +25°C, unless otherwise noted.) (Note 4) PARAMETER SYMBOL Serial Input Data Rate Clock-to-Q Delay tCLK-Q Jitter Peaking JP Jitter Transfer Bandwidth JBW CONDITIONS MIN TYP RATESET = low 2.488 RATESET = high 2.67 Figure 2 (Note 5) -70 MAX UNITS Gbps +70 ps f ≤ 2MHz 0.1 dB RATESET = Low 2.
PAGE 4
MAX3873A Low-Power, Compact 2.5Gbps or 2.7Gbps Clock-Recovery and Data-Retiming IC AC ELECTRICAL CHARACTERISTICS (continued) (VCC = 3.0V to 3.6V, CF = 0.022µF, TA = -40°C to +85°C. Typical values are at VCC = 3.3V, 2.488Gbps, TA = +25°C, unless otherwise noted.) (Note 4) Note 1: At TA = -40°C, DC characteristics are guaranteed by design and characterization. Note 2: CML outputs open. Note 3: RL = 50Ω to VCC. Note 4: AC characteristics are guaranteed by design and characterization.
PAGE 5
Low-Power, Compact 2.5Gbps or 2.7Gbps Clock-Recovery and Data-Retiming IC RECOVERED CLOCK AND DATA (2.488Gbps, 223 - 1 PATTERN, VIN = 50mVP-P) MAX3873A toc02 MAX3873A toc01 RECOVERED CLOCK AND DATA (2.67Gbps, 223 - 1 PATTERN, VIN = 50mVP-P) 125mV/div 125mV/div 100ps/div 100ps/div RECOVERED CLOCK JITTER (2.488Gbps) JITTER TOLERANCE (2.488Gbps, 223 - 1 PATTERN, VIN = 50mVP-P) MAX3873A toc04 MAX3873A toc03 100 INPUT JITTER (UIp-p) WITH 0.2UI OF PWD WITH 0.
PAGE 6
Typical Operating Characteristics (continued) (TA = +25°C, unless otherwise noted.) BIT-ERROR RATIO vs. INPUT AMPLITUDE PULLIN RANGE (RATESET = 0) 2.8 MAX3873A toc09 2.9 10-3 10-4 2.7 BIT ERROR RATIO 2.6 2.5 2.4 10-5 10-6 10-7 2.3 10-8 2.2 10-9 2.1 10-10 2.0 -50 0 50 100 4 5 fJITTER = 10MHz 0.5 0.4 0.3 0.2 PRBS = 223 - 1 0.9 fJITTER = 1MHz PRBS = 223 - 1 0.8 0.7 0.6 0.5 fJITTER = 10MHz 0.4 0.3 0.2 0.1 INPUT DATA FILTERED BY 1870MHz 4TH-ORDER BESSEL FILTER 0 0 0.10 1.
PAGE 7
Low-Power, Compact 2.5Gbps or 2.7Gbps Clock-Recovery and Data-Retiming IC PIN NAME FUNCTION 10 SCLKEN Clock Output Enable, TTL Input. When SCLKEN = open or SCLKEN = high, the clock outputs (SCLKO±) are enabled. When SCLKEN = low, the clock outputs are disabled and SCLKO± = VCC. 11 SCLKO- Negative Clock Output, CML. This output can be disabled by setting SCLKEN to low. 12 SCLKO+ Positive Clock Output, CML. This output can be disabled by setting SCLKEN to low.
PAGE 8
The loop filter output controls the on-chip LC VCO running at either 2.488GHz or 2.67GHz. The VCO provides low phase noise and is trimmed to the correct frequency. Clock jitter generation is typically 2psRMS within a jitter band of 12kHz to 20MHz. Loss-of-Lock Monitor A loss-of-lock (LOL) monitor is incorporated in the MAX3873A to indicate either a loss of frequency lock or the absence of incoming data. Under loss-of-lock conditions, LOL may momentarily assert high due to noise.
PAGE 9
Low-Power, Compact 2.5Gbps or 2.7Gbps Clock-Recovery and Data-Retiming IC The MAX3873A has excellent jitter tolerance. Adding DJ to the input will close the eye opening and result in reduced sinusoidal jitter tolerance. It typically can tolerate more than 0.3UIP-P of 10MHz jitter when measured with a 223 - 1 PRBS data stream with 0.4UI of deterministic jitter (DJ). This gives a total high-frequency jitter tolerance of 0.7UI. Refer to the Jitter Tolerance vs. Pulse-Width Distortion and Jitter Tolerance vs.
PAGE 10
Low-Power, Compact 2.5Gbps or 2.7Gbps Clock-Recovery and Data-Retiming IC MAX3873A Typical Application Circuit SWITCH CARD 2.5Gbps OPTICAL TRANSCEIVER MAX3873A CDR CROSSPOINT SWITCH SDI+ FIL+ FIL- LOL MODE SDI- MAX3873A FASTRACK RATESET 20-PIN QFN SDO+ SDOSCLKO+ SCLKOSCLKEN Chip Information TRANSISTOR COUNT: 2028 PROCESS: SiGe BiCMOS Package Information For the latest package outline information, go to www.maxim-ic.com/packages. PACKAGE TYPE DOCUMENT NO.