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General Description

The MAX3885 deserializer is ideal for converting

2.488Gbps serial data to 16-bit wide, 155Mbps parallel

data in SDH/SONET applications. Operating from a sin-

gle +3.3V supply, this device accepts PECL serial

clock and data inputs, and delivers low-voltage differ-

ential-signal (LVDS) clock and data outputs for interfac-

ing with high-speed digital circuitry. It also provides an

LVDS synchronization input that enables data realign-

ment and reframing. The MAX3885 is available in the

extended temperature range (-40°C to +85°C) in a 64-

pin TQFP package.

Applications

2.488Gbps SDH/SONET Transmission Systems

Add/Drop Multiplexers

Digital Cross Connects

Features

♦♦

Single +3.3V Supply

♦♦

2.488Gbps Serial to 155Mbps Parallel Conversion

♦♦

660mW Operating Power

♦♦

LVDS Data Outputs and Synchronization Inputs

♦♦

Self-Biasing PECL Inputs Ease AC Coupling

♦♦

Synchronization Inputs for Data Realignment and

Reframing

MAX3885

+3.3V, 2.488Gbps, SDH/SONET

1:16 Deserializer with LVDS Outputs

________________________________________________________________

Maxim Integrated Products

19-4767; Rev 4; 12/07

Pin Configuration appears at end of data sheet.

Ordering Information

Typical Operating Circuit

MAX3875

MAX3885

DATA

AND

CLOCK

RECOVERY

SERIAL DATA

INPUTS

OVERHEAD

TERMINATION

100Ω*

= +3.3V

PD15+

PD15-

SD+

SD-

*REQUIRED ONLY IF OVERHEAD CIRCUIT DOES NOT INCLUDE INTERNAL INPUT TERMINATION.

THIS SYMBOL REPRESENTS A TRANSMISSION LINE OF CHARACTERISTIC IMPEDANCE Z

= 50Ω.

GND

133Ω 133Ω

86.6Ω

= +3.3V

133Ω 133Ω

86.6Ω

= +3.3V

SCLK+

SCLK-

PD0+

•

PD0-

PCLK+

PCLK-

SYNC+

SYNC-

PART TEMP RANGE PIN-PACKAGE

MAX3885ECB -40°C to +85°C 64 TQFP

MAX3885ECB+ -40°C to +85°C 64 TQFP

Denotes a lead-free package.

EVALUATION KIT

AVAILABLE

Summary of content (8 pages)

PAGE 1
9-4767; Rev 4; 12/07 KIT ATION EVALU E L B AVAILA +3.3V, 2.488Gbps, SDH/SONET 1:16 Deserializer with LVDS Outputs Features ♦ Single +3.3V Supply The MAX3885 deserializer is ideal for converting 2.488Gbps serial data to 16-bit wide, 155Mbps parallel data in SDH/SONET applications. Operating from a single +3.3V supply, this device accepts PECL serial clock and data inputs, and delivers low-voltage differential-signal (LVDS) clock and data outputs for interfacing with high-speed digital circuitry.
PAGE 2
MAX3885 +3.3V, 2.488Gbps, SDH/SONET 1:16 Deserializer with LVDS Outputs ABSOLUTE MAXIMUM RATINGS Positive Supply Voltage (VCC)...............................-0.5V to +7.0V Input Voltage Level (all inputs)...................-0.5V to (VCC + 0.5V) Output Current LVDS outputs .............................................10mA Continuous Power Dissipation (TA = +85°C) TQFP (derate 24mW/°C above +85°C) .......................1000mW Operating Temperature Range ...........................
PAGE 3
+3.3V, 2.488Gbps, SDH/SONET 1:16 Deserializer with LVDS Outputs 4.2 4.1 SERIAL DATA-HOLD TIME (ps) SERIAL DATA-SETUP TIME (ps) VCC = 3V 0 MAX3885-02 100 MAX3885-01 VCC = 3.6V 4.3 80 60 40 20 0 25 50 75 100 -50 TEMPERATURE (°C) -25 0 25 50 75 -25 VCC = 3V 150 100 25 50 TEMPERATURE (°C) 75 100 PCLK TO DATA OUTPUT PROPAGATION DELAY (ps) VCC = 3.6V 200 0 25 50 75 100 TEMPERATURE (°C) PARALLEL CLOCK TO DATA OUTPUT PROPAGATION DELAY vs.
PAGE 4
+3.3V, 2.488Gbps, SDH/SONET 1:16 Deserializer with LVDS Outputs MAX3885 Pin Description PIN NAME FUNCTION 1, 2, 8, 16, 17, 24, 32, 33, 41, 48, 49, 57, 64 GND Ground 3, 5, 7, 9, 11, 13, 25, 34, 42, 47, 56 VCC +3.3V Supply Voltage 4 SD+ Serial Data Noninverting PECL Input. Data is clocked on the SCLK signal’s positive transition. 6 SD- Serial Data Inverting PECL Input. Data is clocked on the SCLK signal’s positive transition.
PAGE 5
+3.3V, 2.488Gbps, SDH/SONET 1:16 Deserializer with LVDS Outputs The MAX3885 deserializer uses a 16-bit shift register, 16-bit parallel output register, 4-bit counter, PECL input buffers, and low-voltage differential-signal (LVDS) input/output buffers to convert 2.488Gbps serial data to 16-bit wide, 155Mbps parallel data (Figure 2).
PAGE 6
MAX3885 +3.3V, 2.488Gbps, SDH/SONET 1:16 Deserializer with LVDS Outputs tSCLK = 1 / fSCLK SCLK tSU tH SD PCLK tCLK-Q PD0–PD15 NOTE: SIGNALS SHOWN ARE DIFFERENTIAL. FOR EXAMPLE, SCLK = (SCLK+) - (SCLK-). Figure 4. Timing Parameters DC termination between the inverting and noninverting outputs for proper operation. Do not terminate these outputs to ground.
PAGE 7
+3.3V, 2.
PAGE 8
MAX3885 +3.3V, 2.488Gbps, SDH/SONET 1:16 Deserializer with LVDS Outputs Revision History REVISION NUMBER REVISION DATE 0 9/98 1 9/98 PAGES CHANGED DESCRIPTION Initial release. — Updated Typical Operating Circuit 1 Updated Figure 3. 5 2 1/99 Corrected Figure 3. 5 3 2/07 Added lead-free package to Ordering Information table. 1 4 12/07 Replaced package drawing with table.