Datasheet

Ambient and Infrared Proximity Sensor
Bit Transfer
One data bit is transferred during each SCL cycle. The
data on SDA must remain stable during the high period
of the SCL pulse. Changes in SDA while SCL is high are
control signals. See the START and STOP Conditions sec-
tion. SDA and SCL idle high when the I
2
C bus is not busy.
START and STOP Conditions
SDA and SCL idle high when the bus is not in use. A
master initiates communication by issuing a START con-
dition. A START condition is a high-to-low transition on
SDA with SCL high. A STOP condition is a low-to-high
transition on SDA while SCL is high (Figure 5). A START
condition from the master signals the beginning of a
transmission to the IC. The master terminates transmis-
sion, and frees the bus by issuing a STOP condition. The
bus remains active if a Repeated START condition is
generated instead of a STOP condition.
Early STOP Conditions
The IC recognizes a STOP condition at any point during
data transmission except if the STOP condition occurs in
the same high pulse as a START condition. For proper
operation, do not send a STOP condition during the
same SCL high pulse as the START condition.
Acknowledge
The acknowledge bit (ACK) is a clocked 9th bit that the
IC uses to handshake receipt of each byte of data when
in write mode (Figure 6). The IC pulls down SDA dur-
ing the entire master-generated ninth clock pulse if the
previous byte is successfully received. Monitoring ACK
allows for detection of unsuccessful data transfers. An
unsuccessful data transfer occurs if a receiving device
is busy or if a system fault has occurred. In the event of
an unsuccessful data transfer, the bus master can retry
communication. The master pulls down SDA during the
ninth clock cycle to acknowledge receipt of data when
the IC is in read mode. An acknowledge is sent by the
master after each read byte to allow data transfer to
continue. A not acknowledge is sent when the master
reads the final byte of data from the IC, followed by a
STOP condition.
Figure 4. 2-Wire Interface Timing Diagram
Figure 5. START, STOP, and Repeated START Conditions Figure 6. Acknowledge
SCL
SDA
START
CONDITION
STOP
CONDITION
REPEATED
START CONDITION
START
CONDITION
t
HD,STA
t
SU,STA
t
HD,STA
t
SP
t
BUF
t
SU,STO
t
LOW
t
SU,DAT
t
HD,DAT
t
HIGH
t
R
t
F
SCL
SDA
SS
rP
1
SCL
START
CONDITION
SDA
289
CLOCK PULSE FOR
ACKNOWLEDGMENT
ACKNOWLEDGE
NOT ACKNOWLEDGE
MAX44000
Maxim Integrated
19