Datasheet

DESIGNATION QTY DESCRIPTION
J1 1
12-pin (2 x 6) right-angle male
header
J2 1
10-pin (2 x 5) straight male
header
R1–R8 8
150I Q5% resistors (0603)
U1 1
8-channel relay driver
(20 TQFN-EP*)
Maxim MAX4824ETP+
— 1 PCB: EPCB4824PM1
SUPPLIER PHONE WEBSITE
Murata Electronics North America, Inc. 770-436-1300 www.murata-northamerica.com
TDK Corp. 847-803-6100 www.component.tdk.com
DESIGNATION QTY DESCRIPTION
C1 1
1FF Q10%, 10V X7R ceramic
capacitor (0603)
TDK C1608X7R1A105K
C2 1
0.1FF Q10%, 16V X7R ceramic
capacitor (0603)
Murata GRM188R71C104KA01D
C3 1
2.2FF Q10%, 10V X5R ceramic
capacitor (0603)
TDK C1608X5R1A225K/0.80
PIN SIGNAL DESCRIPTION
1
CS
Chip-select input. This active-low
signal latches in the values of LVL and
A2, A1, A0.
2 LVL
Level input. When latched by CS, this
signal determines whether a relay at a
given address (A2, A1, A0) is active.
3 A1 A1 input. Relay address bit 1.
4 A0 A0 input. Relay address bit 0.
5 GND Ground
6 VCC Power supply
7 A2 A2 input. Relay address bit 2.
8
RES
Reset Input. This active-low pin sets all
eight relays inactive.
9
SET
Set Input. This active-low pin sets all
eight relays active.
10 PSAVE
Reduces coil current to relay
hold-current threshold.
11 GND Ground
12 VCC Power supply
_________________________________________________________________ Maxim Integrated Products 2
MAX4824PMB1 Peripheral Module
Component Suppliers
Note: Indicate that you are using the MAX4824PMB1 when contacting these component suppliers.
Component List
Detailed Description
GPIO Interface
The MAX4824PMB1 peripheral module can interface to
the host by plugging directly into a Pmod-compatible
port (configured for GPIO) through connector J1.
J1 provides connection of the module to the Pmod host
through an interface similar to the Pmod Type 1 standard
recommended by Digilent, but incorporates a 12in con-
nector with eight I/O pins. See Table 1.
The J2 connector provides the connection to the open-
drain relay outputs. See Table 2.
Software and FPGA Code
Example software and drivers are available that execute
directly without modification on several FPGA develop-
ment boards, which support an integrated or synthe-
sized microprocessor. These boards include the Digilent
Nexys 3, Avnet LX9, and Avnet ZEDBoard, although
other platforms can be added over time. Maxim provides
complete Xilinx ISE projects containing HDL, Platform
Studio, and SDK projects. In addition, a synthesized bit
stream, ready for FPGA download, is provided for the
demonstration application.
Table 1. Connector J1
(GPIO Communication)
*EP = Exposed pad.