Datasheet

ManualsBrandsMAXIM INTEGRATED ManualsData collecting ICsData acquisition IC - DA converter (DAC) PDIP 16

For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800

_______________General Description

The MAX500 is a quad, 8-bit, voltage-output digital-to-

analog converter (DAC) with a cascadable serial inter-

face. The IC includes four output buffer amplifiers and

input logic for an easy-to-use, two- or three-wire serial

interface. In a system with several MAX500s, only one

serial data line is required to load all the DACs by cas-

cading them. The MAX500 contains double-buffered

logic and a 10-bit shift register that allows all four DACs

to be updated simultaneously using one control signal.

There are three reference inputs so the range of two of

the DACs can be independently set while the other two

DACs track each other.

The MAX500 achieves 8-bit performance over the full

operating temperature range without external trimming.

________________________Applications

Minimum Component Count Analog Systems

Digital Offset/Gain Adjustment

Industrial Process Control

Arbitrary Function Generators

Automatic Test Equipment

____________________________Features

♦ Buffered Voltage Outputs

♦ Double-Buffered Digital Inputs

♦ Microprocessor and TTL/CMOS Compatible

♦ Requires No External Adjustments

♦ Two- or Three-Wire Cascadable Serial Interface

♦ 16-Pin DIP/SO Package and 20-Pin LCC

♦ Operates from Single or Dual Supplies

______________Ordering Information

MAX500

CMOS, Quad, Serial-Interface

8-Bit DAC

________________________________________________________________

Maxim Integrated Products

TOP VIEW

OUT

VREFC

REF

A/B

OUT

MAX500

REF

SRO

SCL

LOAD

SDA

LDAC

DGND

AGND

DIP/SO

_________________Pin Configurations

MAX500

OUT

DAC A

DAC B

DAC C

DAC D

REF

A/B

DAC

REG A

INPUT

REG A

DAC

REG B

INPUT

REG B

DAC

REG C

INPUT

REG C

DAC

REG D

INPUT

REG D

10/11-

BIT

SHIFT

CONTROL

LOGIC

LOAD

SCL

SDA

OUT

SRO

DGND V

AGND

REF

DATA BUS

LDAC

________________Functional Diagram

19-1016; Rev 2; 2/96

PART

MAX500ACPE

MAX500BCPE

MAX500ACWE

0°C to +70°C

TEMP. RANGE PIN-PACKAGE

16 Plastic DIP

16 Wide SO

MAX500BCWE

0°C to +70°C 16 Wide SO

MAX500BC/D 0°C to +70°C Dice*

MAX500AEPE -40°C to +85°C 16 Plastic DIP

MAX500BEPE -40°C to +85°C 16 Plastic DIP

MAX500AEWE

-40°C to +85°C 16 Wide SO

MAX500BEWE

-40°C to +85°C 16 Wide SO

MAX500AEJE -40°C to +85°C 16 CERDIP

MAX500BEJE -40°C to +85°C 16 CERDIP

MAX500AMJE

-55°C to +125°C 16 CERDIP

MAX500BMJE

-55°C to +125°C 16 CERDIP

ERROR (LSB)

±1

±2

±1

±2

±1

±2

±1

±2

±1

±2

±1

±2

*Contact factory for dice specifications.

Pin Configurations continued on last page.

MAX500AMLP

-55°C to +125°C 20 LCC

±1

MAX500BMLP

-55°C to +125°C 20 LCC

±2

Summary of content (12 pages)

PAGE 1
9-1016; Rev 2; 2/96 CMOS, Quad, Serial-Interface 8-Bit DAC The MAX500 is a quad, 8-bit, voltage-output digital-toanalog converter (DAC) with a cascadable serial interface. The IC includes four output buffer amplifiers and input logic for an easy-to-use, two- or three-wire serial interface. In a system with several MAX500s, only one serial data line is required to load all the DACs by cascading them.
PAGE 2
MAX500 CMOS, Quad, Serial-Interface 8-Bit DAC ABSOLUTE MAXIMUM RATINGS Power Requirements VDD to AGND...........................................................-0.3V, +17V VDD to DGND ..........................................................-0.3V, +17V VSS to DGND ..................................................-7V, (VDD + 0.3V) VDD to VSS ...............................................................-0.3V, +24V Digital Input Voltage to DGND ....................-0.3V, (VDD + 0.3V) VREF to AGND ........
PAGE 3
CMOS, Quad, Serial-Interface 8-Bit DAC (VDD = +11.4V to +16.5V, VSS = -5V ±10%, AGND = DGND = 0V, VREF = +2V to (VDD - 4V), TA = TMIN to TMAX, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN TYP 3 8 MAX UNITS DYNAMIC PERFORMANCE Voltage Output Slew Rate TA = +25°C (Note 2) V/µs VOUT Settling Time To ±1/2LSB, VREF = 10V, VDD = +15V, 2kΩ in parallel with 100pF load (Note 2) 2.
PAGE 4
ELECTRICAL CHARACTERISTICS—Single Supply (VDD = +15V ±5%, VSS = AGND = DGND = 0V, VREF = 10V, TA = TMIN to TMAX, unless otherwise noted.
PAGE 5
CMOS, Quad, Serial-Interface 8-Bit DAC SUPPLY CURRENT (mA) RO ≅ 200Ω 12 ISINK (mA) 10 VSS = 0V 10 8 6 4 2.0 IDD 8 6 4 2 0 -2 ISS 1.0 0.0 -1.0 -4 0 -6 -2.0 4 8 6 -55 10 -25 VOUT (V) 0 _______________Detailed Description The MAX500 has four matched voltage-output digital-toanalog converters (DACs). The DACs are “inverted” R-2R ladder networks which convert 8 digital bits into equivalent analog output voltages in proportion to the applied reference voltage(s).
PAGE 6
MAX500 CMOS, Quad, Serial-Interface 8-Bit DAC POSITIVE STEP (VSS = -5V or 0V) NEGATIVE STEP (VSS = -5V or 0V) LDAC 5V/div LDAC 5V/div INPUT (5V/div) OUTPUT 100mV/div OUTPUT 100mV/div OUTPUT (20mV/div) 1µs/div 1µs/div Figure 2. Positive and Negative Settling Times VDD DYNAMIC RESPONSE (VSS = -5V or 0V) LDAC 5V/div FROM INVERTED DAC OUTPUT (+) OUTPUT 5V/div NPN EMITTER FOLLOWER PULL-UP PMOS (-) VOUT INPUTS CC NMOS ACTIVE PULL-DOWN CIRCUIT 2µs/div Figure 3. Dynamic Response VSS Figure 4.
PAGE 7
CMOS, Quad, Serial-Interface 8-Bit DAC D7 MSB A0 SCL D6 D5 D4 D3 D0 LSB D1 D2 MAX500 A1 SDA LOAD LDAC SRO (SERIAL OUTPUT) t1 t2 SCL SCL tS1 SDA tLDS tH tLDW LOAD LDAC SRO tLDS tD1 tLDAC Figure 5. 3-Wire Mode A1 A0 SCL D7 MSB D6 D5 D4 D3 D2 D0 LSB D1 SDA LDAC SRO (SERIAL OUTPUT) t2 t1 SCL SCL tS2 tS3 tS1 SDA SDA tD1 SRO tD1 tLDS LDAC tLDAC Figure 6.
PAGE 8
MAX500 CMOS, Quad, Serial-Interface 8-Bit DAC A low level on LOAD line initiates the transfer of data from the shift register to the addressed input register. The data can stay in this register until all four of the input registers are updated. Then all of the DAC registers can be simultaneously updated using the LDAC (load DAC) signal. When LDAC is low, the input register’s data is loaded into the DAC registers (see Figure 5 for timing diagram).
PAGE 9
CMOS, Quad, Serial-Interface 8-Bit DAC ground buses within one diode drop of each other. To avoid parasitic device turn-on, AGND must not be allowed to be more negative than DGND. DGND should be used as supply ground for bypassing purposes. REFERENCE INPUTS 4 12 13 +15V 14 VDD VREFA/B VREFC VREFD __________Applications Information 2 DAC A Power-Supply and Reference Operating Ranges The MAX500 is fully specified to operate with V DD between +12V ±5% and +15V ±10% (+11.4V to +16.
PAGE 10
MAX500 CMOS, Quad, Serial-Interface 8-Bit DAC Table 3. Unipolar Code Table DAC CONTENTS Table 4.
PAGE 11
CMOS, Quad, Serial-Interface 8-Bit DAC Generating VSS The performance of the MAX500 is specified for both dual and single-supply (VSS = 0V) operation. When the improved performance of dual-supply operation is desired, but only a single supply is available, a -5V VSS supply can be generated using an ICL7660 in one of the circuits of Figure 12.
PAGE 12
A15 A8 A15 A0 ADDRESS BUS 8085/ 8088 A0 82C55 PA0 A1 PA1 CS PA2 WR ADDRESS DECODE WR EN LATCH ALE AD7 AD0 D7 D0 PA3 . . SCL MAX500 SDA LDAC LOAD* 6809/ 6502 R/W Θ OR E ∆7 D0 ADDRESS AND DATA BUS * CONNECT LOAD TO P1.3 FOR 3-WIRE MODE OR CONNECT LOAD TO VDD FOR 2-WIRE MODE ADDRESS BUS 6821 6521 PA0 C32 PA1 R/W PA2 E DB7 PA3 . . DB0 ADDRESS DECODE SCL MAX500 SDA LDAC LOAD* DATA BUS * CONNECT LOAD TO P1.3 FOR 3-WIRE MODE OR CONNECT LOAD TO VDD FOR 2-WIRE MODE Figure 15.