Datasheet

MAX5075
Push-Pull FET Driver with Integrated Oscillator
and Clock Output
_______________________________________________________________________________________ 5
Pin Description
PIN NAME FUNCTION
1 CLK
Synchronizing Clock Output. Clock output with a ±10mA peak current drive that can be used to
synchronize an external PWM regulator. CLK/NDRV1 frequency has a 1x, 2x, or 4x ratio. See the
Synchronizing Clock Output section.
2 I.C. Internal Connection. Connect to ground. Internal function.
3RT
Oscillator Timing Resistor Connection. Bypass RT with a series combination of a 4.7kΩ resistor and a
1nF capacitor to DGND. Connect a resistor from RT to DGND to set the internal oscillator.
4 DGND Digital Ground. Connect DGND to ground plane.
5 PGND Power Ground. Connect PGND to ground plane.
6 NDRV1 Gate Driver 1. Connect NDRV1 to the gate of the external n-channel FET.
7 NDRV2 Gate Driver 2. Connect NDRV2 to the gate of the external n-channel FET.
8V
CC
Power-Supply Input. Bypass V
CC
to PGND with 0.1µF||1µF ceramic capacitors.
EP EP Exposed Pad. Internally connected to DGND. Connect exposed pad to ground plane.
NDRV1
PGND
V
CC
NDRV2
T-FF
UVLO 3.5V
Q
Q
CLK
RT
DGND
OSC
I.C.
5V
LDO
V
CC
A (1x)
B (2x)
C (4x)
MAX5075
Q
Q
Q
Q
INTERNAL
FUNCTION
Figure 1. MAX5075 Functional Diagram