Datasheet

Power Dissipation
The power dissipation of the MAX5075 is a function of
the sum of the quiescent current and the output current
(either capacitive or resistive load). Maintain the sum of
the currents so the maximum power dissipation limit is
not exceeded. The power dissipation (P
DISS
) due to the
quiescent switching supply current (I
CCSW
) can be cal-
culated as:
P
DISS
= V
CC
x I
CCSW
For capacitive loads, use the following equation to esti-
mate the power dissipation:
P
LOAD
= 2 x C
LOAD
x V
CC
2
x f
NDRV_
where C
LOAD
is the capacitive load at NDRV1 and
NDRV2, V
CC
is the supply voltage, and f
NDRV_
is the
MAX5075 NDRV_ switching frequency.
Calculate the total power dissipation (P
T
) as follows:
P
T
= P
DISS
+ P
LOAD
Layout Recommendations
The MAX5075 sources and sinks large currents that can
create very fast rise and fall edges at the gate of the
switching MOSFETs. The high di/dt can cause unaccept-
able ringing if the trace lengths and impedances are not
well controlled. Use the following PC board layout guide-
lines when designing with the MAX5075:
• Place one or more 0.1µF decoupling ceramic
capacitors from V
CC
to PGND as close to the
device as possible. Connect V
CC
and all ground
pins to large copper areas. Place one bulk capaci-
tor of 10µF on the PC board with a low-impedance
path to the V
CC
input and PGND of the MAX5075.
• Two AC current loops form between the device and
the gate of the driven MOSFETs. The MOSFETs
look like a large capacitance from gate to source
when the gate pulls low. The current loop is from
the MOSFET gate to NDRV1 and NDRV2 of the
MAX5075, to PGND, and to the source of the
MOSFET. When the gate of the MOSFET pulls high,
the current is from the V
CC
terminal of the decou-
pling capacitor, to V
CC
of the MAX5075, to NDRV1
and NDRV2, and to the MOSFET gate and source.
Both charging current and discharging current loops
are important. Minimize the physical distance and
the impedance in these AC current paths.
• Keep the device as close to the MOSFET as possible.
Chip Information
TRANSISTOR COUNT: 1335
PROCESS: BiCMOS
MAX5075
Push-Pull FET Driver with Integrated Oscillator
and Clock Output
_______________________________________________________________________________________ 7
1
2
3
4
8
7
6
5
V
CC
NDRV2
NDRV1
PGNDDGND
RT
I.C.
CLK
*EP
*EXPOSED PADDLE CONNECTED TO DGND.
MAX5075
µMAX
TOP VIEW
Pin Configuration