Datasheet

ManualsBrandsMAXIM INTEGRATED ManualsData collecting ICsData acquisition IC - DA converter (DAC) TSSOP 20

For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800.

For small orders, phone 1-800-835-8769.

General Description

The MAX5100 parallel-input, voltage-output, quad 8-bit

digital-to-analog converter (DAC) operates from a sin-

gle +2.7V to +5.5V supply and comes in a space-sav-

ing 20-pin TSSOP package. Internal precision buffers

swing Rail-to-Rail

, and the reference input range

includes both ground and the positive rail. All four

DACs share a common reference input.

The MAX5100 provides double-buffered logic inputs:

four 8-bit buffer registers followed by four 8-bit DAC

registers. This keeps the DAC outputs from changing

during the write operation. An asynchronous control

pin, LDAC, allows for simultaneous updating of the

DAC registers.

The MAX5100 features a shutdown mode that reduces

current to 1nA, as well as a power-on reset mode that

resets all registers to code 00 hex on power-up.

Applications

Digital Gain and Offset Adjustments

Programmable Attenuators

Portable Instruments

Power-Amp Bias Control

Features

♦ +2.7V to +5.5V Single-Supply Operation

♦ Ultra-Low Supply Current

0.4mA while Operating

1nA in Shutdown Mode

♦ Ultra-Small 20-Pin TSSOP Package

♦ Ground to V

Reference Input Range

♦ Output Buffer Amplifiers Swing Rail-to-Rail

♦ Double-Buffered Registers for Synchronous

Updating

♦ Power-On Reset Sets All Registers to Zero

MAX5100

+2.7V to +5.5V, Low-Power, Quad, Parallel

8-Bit DAC with Rail-to-Rail Voltage Outputs

________________________________________________________________ Maxim Integrated Products 1

OUTC

OUTD

GND

A0REF

OUTA

OUTB

TOP VIEW

LDAC

D1D6

SHDN

D3D4

MAX5100

TSSOP

19-1557; Rev 0; 10/99

PART

MAX5100AEUP

MAX5100BEUP -40°C to +85°C

-40°C to +85°C

TEMP. RANGE PIN-PACKAGE

20 TSSOP

Pin Configuration

Ordering Information

Rail-to-Rail is a registered trademark of Nippon Motorola, Ltd.

INL

(LSB)

±1

±2

Summary of content (8 pages)

PAGE 1
9-1557; Rev 0; 10/99 +2.7V to +5.5V, Low-Power, Quad, Parallel 8-Bit DAC with Rail-to-Rail Voltage Outputs The MAX5100 provides double-buffered logic inputs: four 8-bit buffer registers followed by four 8-bit DAC registers. This keeps the DAC outputs from changing during the write operation. An asynchronous control pin, LDAC, allows for simultaneous updating of the DAC registers.
PAGE 2
MAX5100 +2.7V to +5.5V, Low-Power, Quad, Parallel 8-Bit DAC with Rail-to-Rail Voltage Outputs ABSOLUTE MAXIMUM RATINGS VDD to GND ..............................................................-0.3V to +6V D_, A_, WR, SHDN, LDAC to GND...........................-0.3V to +6V REF to GND ................................................-0.3V to (VDD + 0.3V) OUT_ to GND ...........................................................-0.3V to VDD Maximum Current into Any Pin .........................................
PAGE 3
+2.7V to +5.5V, Low-Power, Quad, Parallel 8-Bit DAC with Rail-to-Rail Voltage Outputs (VDD = VREF = +2.7V to +5.5V, RL = 10kΩ, CL = 100pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at VDD = VREF = +3V and TA = +25°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS DYNAMIC PERFORMANCE 0.6 V/µs 6 µs Code 00 to code FF hex 500 nVs Digital Feedthrough (Note 5) Code 00 to code FF hex 0.
PAGE 4
MAX5100 +2.7V to +5.5V, Low-Power, Quad, Parallel 8-Bit DAC with Rail-to-Rail Voltage Outputs ADDRESS ADDRESS VALID tWR tAS tAH- WR tLD LDAC (NOTE 8) tDS- tDH- DATA DATA VALID Figure 1. Timing Diagram Typical Operating Characteristics (VDD = VREF = +3V, RL = 10kΩ, CL = 100pF, code = FF hex, TA = +25°C, unless otherwise noted.) 5 4 VDD = VREF = 3V VOUT (V) 0.6 VDD = VREF = 5V 0.
PAGE 5
+2.7V to +5.5V, Low-Power, Quad, Parallel 8-Bit DAC with Rail-to-Rail Voltage Outputs REFERENCE INPUT FREQUENCY RESPONSE -30 REF = 0.5Vp-p -50 REF = 1Vp-p -60 MAX5100 toc08 CH1 = LDAC, 2V/div CH2 = VOUTA, 50mV/div, AC-COUPLED DAC CODE FROM 80 TO 7F HEX -20 1 -30 -40 -50 2 -60 -70 CODE = FF HEX, REF IS 1Vp-p SIGNAL VREF = 1.5V -80 -90 -80 10 0.01 100 0.
PAGE 6
+2.7V to +5.5V, Low-Power, Quad, Parallel 8-Bit DAC with Rail-to-Rail Voltage Outputs MAX5100 Pin Description PIN NAME FUNCTION 1 OUTB DAC B Voltage Output 2 OUTA DAC A Voltage Output 3 VDD Positive Supply Voltage. Bypass VDD to GND using a 0.1µF capacitor. 4 REF Reference Voltage Input 5 SHDN 6 WR 7–14 D7–D0 Data Inputs 7–0 15 LDAC Load DAC Input (active low). Drive the asynchronous LDAC input low to transfer the contents of all input latches to their respective DAC latch.
PAGE 7
+2.7V to +5.5V, Low-Power, Quad, Parallel 8-Bit DAC with Rail-to-Rail Voltage Outputs DAC A LATCH DAC A OUTA INPUT LATCH B DAC B LATCH DAC B OUTB INPUT LATCH C DAC C LATCH DAC C OUTC INPUT LATCH D DAC D LATCH DAC D OUTD MAX5100 INPUT LATCH A D0–D7 AO A1 CONTROL LOGIC WR MAX5100 LDAC REF SHDN Figure 2. Functional Diagram Table 1.
PAGE 8
+2.7V to +5.5V, Low-Power, Quad, Parallel 8-Bit DAC with Rail-to-Rail Voltage Outputs TSSOP.EPS MAX5100 Package Information Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.