Datasheet

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MAX5215/MAX5217

14-/16-Bit, Low-Power, Buffered Output,

Rail-to-Rail DACs with I

C Interface

General Description

The MAX5215/MAX5217 are pin-compatible 14-bit

and 16-bit digital-to-analog converters (DACs). The

MAX5215/MAX5217 are single-channel, low-powered,

buffered voltage-output DACs. The devices use a preci-

sion external reference applied through the high resis-

tance input for rail-to-rail operation and low system power

consumption. The MAX5215/MAX5217 accept a wide

2.7V to 5.5V supply voltage range. Power consumption

is extremely low to accommodate most low-power and

low-voltage applications.

The MAX5215/MAX5217 have an I

C-compatible, 2-wire

serial interface that operates at clock rates up to 400kHz.

On power-up, the MAX5215/MAX5217 reset the DAC out-

put to zero, providing additional safety for applications

that drive valves or other transducers that need to be off

on power-up. The DAC output is buffered resulting in a

low supply current of 80µA (max) and a low offset error

of ±0.25mV. An asynchronous active-low input, AUX,

is provided. This input can be programmed to support

clear or load DAC operations, independent of the serial

interface. The MAX5215/MAX5217 are available in an

ultra-small (3mm x 5mm), 8-pin µMAXM package and are

specified over the -40°C to +105°C extended industrial

temperature range.

Applications

Features

S Low-Power Consumption (80µA, max)

S 18µs Settling Time

S 16-/14-Bit Resolution in a 3mm x 5mm, 8-Pin

µMAX Package

S Relative Accuracy



±0.4 LSB INL (MAX5215, 14 Bit) typ,

1 LSB (max)

±1.2 LSB INL (MAX5217, 16 Bit) typ,

4 LSB (max)

S Guaranteed Monotonic Over All Operating Range

S Low Gain and Offset Error

S Wide 2.7V to 5.5V Supply Range

S Rail-to-Rail Buffered Output Operation

S Safe Power-Up-Reset to Zero DAC Output

S I

C-Compatible 400kHz Serial Interface

S User-Programmable AUX Input Functions



CLR, Clear to 0, Midscale, or Full Scale



LDAC, Asynchronous Load DAC

S 256kI Reference Input Resistance for Low-Power

Operation

S Buffered Voltage Output Directly Drives 10kI

Loads

S Output Power-Down Terminated with 1kI or

100kI to Ground or Left High Impedance

Functional Block Diagram

Ordering Information appears at end of data sheet.

µMAX is a registered trademark of Maxim Integrated Products, Inc.

Remote Sensing

Portable Instrumentation

Communication Systems

Automatic Tuning

Gain and Offset

Adjustment

Power Amplifier Control

Automatic Test Equipment

Process Control and

Servo Loops

Data Acquisition

Programmable Voltage

and Current Sources

19-6469; Rev 0; 11/12

For related parts and recommended products to use with this part, refer to: www.maximintegrated.com/MAX5215.related

EVALUATION KIT AVAILABLE

CODE

C SERIAL

INTERFACE

DAC

AUX = CLR/LDAC

POR

14-/16-BIT

DAC

BUFFER

100kI 1kI

ADDR

SCL

SDA

GND

OUT

REF

( ) FOR AUX CONFIGURED AS CLR

MAX5215

MAX5217

For pricing, delivery, and ordering information, please contact Maxim Direct

at 1-888-629-4642, or visit Maxim’s website at www.maximintegrated.com.

Summary of content (26 pages)

PAGE 1
EVALUATION KIT AVAILABLE MAX5215/MAX5217 14-/16-Bit, Low-Power, Buffered Output, Rail-to-Rail DACs with I2C Interface General Description The MAX5215/MAX5217 are pin-compatible 14-bit and 16-bit digital-to-analog converters (DACs). The MAX5215/MAX5217 are single-channel, low-powered, buffered voltage-output DACs. The devices use a precision external reference applied through the high resistance input for rail-to-rail operation and low system power consumption. The MAX5215/MAX5217 accept a wide 2.7V to 5.
PAGE 2
MAX5215/MAX5217 14-/16-Bit, Low-Power, Buffered Output, Rail-to-Rail DACs with I2C Interface ABSOLUTE MAXIMUM RATINGS VDD to GND..............................................................-0.3V to +6V ADDR, REF, OUT, AUX to GND........-0.3V to the lower of (VDD + 0.3V) and +6V SCL, SDA, to GND...................................................-0.3V to +6V Continuous Power Dissipation (TA = +70NC) FMAX (derate at 4.8mW/NC above 70NC).....................387mW Maximum Current into Any Input or Output......
PAGE 3
MAX5215/MAX5217 14-/16-Bit, Low-Power, Buffered Output, Rail-to-Rail DACs with I2C Interface ELECTRICAL CHARACTERISTICS (continued) (VDD = 2.7V to 5.5V, VREF = 2.5V to VDD, CL = 60pF, RL = 10kI, TA = -40NC to 105NC, unless otherwise noted. Typical values are at TA = +25NC.)(Note 2) PARAMETER SYMBOL Maximum Capacitive Load (No Sustained Oscillations) CL Resistive Load (Note 7) RL CONDITIONS MIN Series resistance = 0I TYP MAX 0.
PAGE 4
MAX5215/MAX5217 14-/16-Bit, Low-Power, Buffered Output, Rail-to-Rail DACs with I2C Interface ELECTRICAL CHARACTERISTICS (continued) (VDD = 2.7V to 5.5V, VREF = 2.5V to VDD, CL = 60pF, RL = 10kI, TA = -40NC to 105NC, unless otherwise noted. Typical values are at TA = +25NC.)(Note 2) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 400 kHz TIMING CHARACTERISTICS SCL Clock Frequency fSCL sBus Free Time Between a STOP and a START Condition tBUF 1.
PAGE 5
MAX5215/MAX5217 14-/16-Bit, Low-Power, Buffered Output, Rail-to-Rail DACs with I2C Interface SDA tLOW tf tSU;DAT tr tHD;STA tf tSP tBUF tr SCL tHD;STA tCLPW S tHIGH tSU;STA tHD;DAT tSU;STO Sr P CLR tLDPW tLDH tCLRSTA S LDAC Figure 1. I2C Serial Interface Timing Diagram Typical Operating Characteristics (VDD = 5V, TA = +25°C, unless otherwise noted.) 0.4 0.2 0.2 0 -0.2 0 -0.4 -0.6 -0.6 -0.8 -0.8 -1.
PAGE 6
MAX5215/MAX5217 14-/16-Bit, Low-Power, Buffered Output, Rail-to-Rail DACs with I2C Interface Typical Operating Characteristics (continued) (VDD = 5V, TA = +25°C, unless otherwise noted.) 1.5 0 -1 MAX5217 0 -0.5 -1.0 0 MIN -0.50 -0.75 -1.00 2.7 DEVICE NUMBER 3.5 3.9 4.3 4.7 SUPPLY VOLTAGE (V) INTEGRAL NONLINEARITY vs. SUPPLY VOLTAGE INTEGRAL NONLINEARITY vs. TEMPERATURE INTEGRAL NONLINEARITY vs. TEMPERATURE 65536 MAX5217 2 1.00 MIN 7 9 11 13 15 17 19 MAX5215 0.50 INL (LSB) 0 5 0.
PAGE 7
MAX5215/MAX5217 14-/16-Bit, Low-Power, Buffered Output, Rail-to-Rail DACs with I2C Interface Typical Operating Characteristics (continued) (VDD = 5V, TA = +25°C, unless otherwise noted.) MAX5215 VREF = 5V 0.3 DIFFERENTIAL NONLINEARITY vs. DIGITAL INPUT CODE MAX5215 VREF = 2.5V 0.5 0.3 MAX5215 toc07c 0.5 MAX5215 toc07a 0.5 DIFFERENTIAL NONLINEARITY vs. DIGITAL INPUT CODE MAX5215 toc07b DIFFERENTIAL NONLINEARITY vs. DIGITAL INPUT CODE MAX5217 VREF = 5V 0.4 0.3 -0.1 0.
PAGE 8
MAX5215/MAX5217 14-/16-Bit, Low-Power, Buffered Output, Rail-to-Rail DACs with I2C Interface Typical Operating Characteristics (continued) (VDD = 5V, TA = +25°C, unless otherwise noted.) 0.75 0.50 MAX5215 0 2 0 0 3.5 3.9 4.3 4.7 5.1 5.5 -40 -20 0 GAIN ERROR vs. SUPPLY -0.02 -0.03 MAX5215 -0.04 DRIFT (µV/°C) GAIN ERROR vs. TEMPERATURE VREF = 2.5V 14 10 -0.02 -0.03 MAX5215 -0.04 3.5 3.9 4.7 5.1 -0.06 5.
PAGE 9
MAX5215/MAX5217 14-/16-Bit, Low-Power, Buffered Output, Rail-to-Rail DACs with I2C Interface Typical Operating Characteristics (continued) (VDD = 5V, TA = +25°C, unless otherwise noted.) 55 MAX5215/MAX5217 NO LOAD VDD = VREF VOUT = ZEROSCALE 40 -40 -20 0 20 40 60 80 68 MAX5215 66 64 2.7 TEMPERATURE (°C) SUPPLY CURRENT (µA) 3.1 3.5 3.9 4.3 0.3 0.2 0.1 NO LOAD VDD = VREF 75 SUPPLY CURRENT (µA) -40°C 0°C +25°C +85°C +105°C 4.7 5.1 MAX5215 70 65 VREF = 5.0V VREF = 2.5V 60 55 3.
PAGE 10
MAX5215/MAX5217 14-/16-Bit, Low-Power, Buffered Output, Rail-to-Rail DACs with I2C Interface Typical Operating Characteristics (continued) (VDD = 5V, TA = +25°C, unless otherwise noted.) MAJOR CODE TRANSITION (0x8000 TO 0x7FFF) MAJOR CODE TRANSITION (0x1FFF TO 0x2000) MAX5215 toc24b MAX5215 toc24c MAX5215 VREF = 5V NO LOAD MAX5217 VREF = 5V NO LOAD OUT = MIDSCALE AC-COUPLED 1mV/div OUT = MIDSCALE AC-COUPLED 1mV/div 4µs/div 4µs/div MAJOR CODE TRANSITION (0x2000 TO 0x1FFF) SETTLING TO ±0.
PAGE 11
MAX5215/MAX5217 14-/16-Bit, Low-Power, Buffered Output, Rail-to-Rail DACs with I2C Interface Typical Operating Characteristics (continued) (VDD = 5V, TA = +25°C, unless otherwise noted.) OUTPUT VOLTAGE vs. OUTPUT CURRENT SUPPLY CURRENT vs. DIGITAL INPUT VOLTAGE 2.40 2.35 2.30 VDD = 5V VREF = 5V 2000 VDDI = 2.7V LOW T0 HIGH 1500 VDD = 2.7V HIGH T0 LOW 1000 0 0 1 2 3 4 5 6 0 -5 -10 -15 500 2.
PAGE 12
MAX5215/MAX5217 14-/16-Bit, Low-Power, Buffered Output, Rail-to-Rail DACs with I2C Interface Pin Configuration TOP VIEW REF 1 ADDR 2 SCL 3 SDA 4 + MAX5215 MAX5217 8 GND 7 VDD 6 OUT 5 AUX µMAX Pin Description PIN NAME 1 REF FUNCTION 2 ADDR 3 SCL I2C Serial Clock Input 4 SDA I2C Serial Data Input 5 AUX User-Configurable Active-Low Asynchronous Input.
PAGE 13
MAX5215/MAX5217 14-/16-Bit, Low-Power, Buffered Output, Rail-to-Rail DACs with I2C Interface The DAC ideal output voltage is defined by: VOUT = VREF x D/2N where D = code loaded into the DAC register, VREF = reference voltage, N = resolution DAC Reference (REF) The external reference input features a typical input impedance of 256kI (independent of the DAC code) and accepts an input voltage from +2V to VDD. Connect an external voltage supply between REF and GND to apply an external reference. Visit www.
PAGE 14
MAX5215/MAX5217 14-/16-Bit, Low-Power, Buffered Output, Rail-to-Rail DACs with I2C Interface I2C Serial Interface is required on SCL if there are multiple masters on the bus, or if the single master has an open-drain SCL output. The MAX5215/MAX5217 feature an I2C/SMBusKcompatible 2-wire serial interface consisting of a serial data line (SDA) and a serial clock line (SCL). SDA and SCL enable communication between the part and the master at clock rates up to 400kHz.
PAGE 15
MAX5215/MAX5217 14-/16-Bit, Low-Power, Buffered Output, Rail-to-Rail DACs with I2C Interface I2C Slave Address The slave address is defined as the seven most significant bits (MSBs) followed by the R/W bit (Figure 1). The 5 MSBs (A[6:2]) are 00111 with the two LSBs (A[1:0]) determined by the input ADDR as shown in Table 1. Setting the R/W bit to 1 configures the MAX5215/MAX5217 for read mode. Setting the R//W bit to 0 configures the MAX5215/ MAX5217 for write mode.
PAGE 16
MAX5215/MAX5217 14-/16-Bit, Low-Power, Buffered Output, Rail-to-Rail DACs with I2C Interface START SDA WRITE BYTE #1: DEVICE ADDRESS WRITE BYTE #2: USER COMMAND WRITE BYTE #3: DATA BYTE #1 WRITE BYTE #4: DATA BYTE #2 0 0 1 1 1 A1 A0 W A R7 R6 R5 R4 R3 R2 R1 R0 A 15 14 13 12 11 10 9 SCL 8 A 7 6 5 4 3 2 A ACK. GENERATED BY MAX5215/MAX5217 STOP 1 0 A COMMAND EXECUTED Figure 4.
PAGE 17
MAX5215/MAX5217 14-/16-Bit, Low-Power, Buffered Output, Rail-to-Rail DACs with I2C Interface WRITE ADDRESS BYTE #1: DEVICE ADDRESS START SDA 0 SCL 0 1 1 WRITE REGISTER NO.
PAGE 18
MAX5215/MAX5217 14-/16-Bit, Low-Power, Buffered Output, Rail-to-Rail DACs with I2C Interface I2C User-Command Register Map This section lists the user-accessible commands and registers for the MAX5215/MAX5217. Table 2 provides detailed information about the Command Registers. No_Op Command (0x00) The No_Op command (Table 3) has no external effect on the device for I2C write. The asynchronous CLR input has no effect on the No_Op command. Table 2.
PAGE 19
MAX5215/MAX5217 14-/16-Bit, Low-Power, Buffered Output, Rail-to-Rail DACs with I2C Interface CODE_LOAD Command (0x01) LOAD Command (0x03) The CODE_LOAD command (Table 4) is the combination of the CODE command and LOAD command. The CODE_LOAD command is executed on the SCL rising edge following the 2nd data byte. Upon its execution, the CODE_LOAD command updates the CODE register and the DAC latch with the user data content provided.
PAGE 20
MAX5215/MAX5217 14-/16-Bit, Low-Power, Buffered Output, Rail-to-Rail DACs with I2C Interface CODE_m Command (0x06) USER_CONFIG Command (0x08) The CODE_m command (Table 8) is the multibyte version of the CODE command. The CODE_m command is initially executed on the SCL rising edge following the 2nd data byte. The command is subsequently executed after each pair of data bytes which follow, for the duration of the operation (see the I2C Write Operation (Multibyte Protocol) section).
PAGE 21
MAX5215/MAX5217 14-/16-Bit, Low-Power, Buffered Output, Rail-to-Rail DACs with I2C Interface SW_RESET Command (0x09) The SW_RESET command (Table 11) resets the CODE register, the DAC latch, and all the configurations programmed via the USER_CONFIG command to the POR default values. The SW_RESET command is executed on the SCL rising edge following the second data byte. The asynchronous CLR input has no effect on the SW_RESET command.
PAGE 22
MAX5215/MAX5217 14-/16-Bit, Low-Power, Buffered Output, Rail-to-Rail DACs with I2C Interface User Read Command Descriptions The MAX5215/MAX5217 allow the user to read back the data for supported registers. Table 13 lists the User Readback commands and the 2 data byte contents being read back. For the MAX5215, CODE and DAC read back, the data content is left justified and the 2 LSBs ([1:0]) of the input 2-byte data are not used and read out as 0.
PAGE 23
MAX5215/MAX5217 14-/16-Bit, Low-Power, Buffered Output, Rail-to-Rail DACs with I2C Interface Definitions Integral Nonlinearity (INL) INL is the deviation of the measured transfer function from a straight line drawn between two codes once offset and gain errors have been nullified. Differential Nonlinearity (DNL) DNL is the difference between an actual step height and the ideal value of 1 LSB. If the magnitude of the DNL is greater than -1 LSB, the DAC guarantees no missing codes and is monotonic.
PAGE 24
MAX5215/MAX5217 14-/16-Bit, Low-Power, Buffered Output, Rail-to-Rail DACs with I2C Interface Typical Operating Circuit V+ VREF_IN 100nF 4.7µF VREF_OUT MAX6133 100nF VDD AUX V+ OUT DAC VOUT = -VREF TO +VREF VOUT ADDR µC SCL MAX5215 MAX5217 SDA V+ REF VR1 R2 R1 = R2 GND V- BIPOLAR OPERATION V+ VREF_IN 100nF 4.
PAGE 25
MAX5215/MAX5217 14-/16-Bit, Low-Power, Buffered Output, Rail-to-Rail DACs with I2C Interface Ordering Information PIN-PACKAGE RESOLUTION (BITS) INL MAX (LSB) MAX5215GUA+ PART 8 FMAX 14 Q1 MAX5217GUA+ 8 FMAX 16 Q4 MAX5217BGUA+ 8 FMAX 16 Q8 Note: All devices are specified over the -40°C to +105°C operating temperature range. +Denotes a lead(Pb)-free/RoHS-compliant package. R = Tape and reel.
PAGE 26
MAX5215/MAX5217 14-/16-Bit, Low-Power, Buffered Output, Rail-to-Rail DACs with I2C Interface Revision History REVISION NUMBER REVISION DATE 0 11/12 DESCRIPTION Initial release PAGES CHANGED — Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time.