Datasheet

PINS SELECTION
2-1
REF provided by on-board MAX6029EUK25
voltage reference
2-3
REF provided by user through pin 3 of
connector J2
GN D
REF
1
CS
2
SCLK
3
DIN
4
CLR
5
OU T
6
VD D
7
GN D
8
MAX5 216GUA +
U1
SS
MOSI
SCK
GN D
VCC
GN D
VCC
GN D
1
2
3
JP1
Select VREF source
GN D
DA CO UT
VREFIN
SCK
CLR
GN D
15 0R3
1
3
2
EMIFILTF1
GN D
10 uF
C1
GN D
1
2
3
4
5
6
J1
MOSI
SS15 0R1
15 0R2
IN
1
GN D
2
N. C.
3
N. C.
4
OU T
5
MAX6 029 EUK 25+
U2
1u F
C2
0. 1uFC3
0. 1uF
C4
0. 1uF
C5
VCC
VCC
4. 7k
R4
VCC
1
2
3
4
J2
_________________________________________________________________ Maxim Integrated Products 3
MAX5216PMB1 Peripheral Module
Nexys 3, Avnet LX9, and Avnet ZEDBoard, although
other platforms can be added over time. Maxim provides
complete Xilinx ISE projects containing HDL, Platform
Studio, and SDK projects. In addition, a synthesized bit
stream, ready for FPGA download, is provided for the
demonstration application.
The software project (for the SDK) contains several source
files intended to accelerate customer evaluation and design.
These include a base application (maximModules.c) that
demonstrates module functionality and uses an API inter-
face (maximDeviceSpecificUtilities.c) to set and access
Maxim device functions within a specific module.
The source code is written in standard ANSI C format, and
all API documentation including theory/operation, register
description, and function prototypes are documented in
the API interface file (maximDeviceSpecificUtilities.h & .c).
The complete software kit is available for download
www.maxim-ic.com. Quick start instructions are also
available as a separate document.
Table 3. Jumper JP1 (Reference Voltage
Selection)
Figure 1. MAX5216PMB1 Peripheral Module Schematic