Datasheet

ManualsBrandsMAXIM INTEGRATED ManualsData collecting ICsData acquisition IC - DA converter (DAC) QSOP 16

General Description

The MAX5258/MAX5259 are +3V/+5V single-supply,

digital serial-input, voltage-output, 8-bit octal digital-to-

analog converters (DACs). Internal precision buffers

swing Rail-to-Rail

, and the reference input range

extends from ground to the positive supply. The +5V

(MAX5258) and the +3V (MAX5259) feature a 10µA

(max) shutdown mode.

The serial interface is double-buffered. A 16-bit input

shift register is followed by eight 8-bit input registers

and eight 8-bit DAC registers. The 16-bit serial word

consists of two “don’t care” bits, three address bits,

three control bits, and eight data bits. The input and

DAC registers can both be updated independently or

simultaneously with a single software command. The

asynchronous control input (LDAC) provides simultane-

ous updating of all eight DAC registers.

The interface is compatible with SPI™, QSPI™ (CPOL =

CPHA = 0 or CPOL = CPHA = 1), and MICROWIRE™.

A buffered digital data output allows daisy-chaining of

serial devices.

The MAX5258/MAX5259 are available in a 16-pin QSOP

package.

________________________Applications

Digital Gain and Offset Adjustment

Programmable Attenuators

Programmable Current Sources

Portable Instruments

Features

♦ +2.7V to +5.5V Single-Supply Operation

♦ Low Supply Current: 1.3mA

♦ Low-Power Shutdown Mode

0.24µA (MAX5259)

0.45µA (MAX5258)

♦ ±1LSB DNL (max)

♦ ±1LSB INL (max)

♦ Ground to V

Reference Input Range

♦ Output Buffer Amplifiers Swing Rail-to-Rail

♦ 10MHz Serial Interface, SPI, QSPI (CPOL = CPHA

= 0 or CPOL = CPHA = 1), and MICROWIRE-

Compatible

♦ Double-Buffered Registers for Synchronous

Updating

♦ Serial Data Output for Daisy-Chaining

♦ Ultra-Small 16-Pin QSOP Package

+3V/+5V, Low-Power, 8-Bit Octal DACs

with Rail-to-Rail Output Buffers

________________________________________________________________ Maxim Integrated Products 1

OUTB OUTC

OUTD

DOUT

DIN

SCLK

OUTH

OUTG

TOP VIEW

MAX5258

MAX5259

QSOP

OUTA

OUTE

OUTF

GND

REF

LDAC

Pin Configuration

19-1844; Rev 1; 4/01

EVALUATION KIT

AVAILABLE

Ordering Information

PART

TEMP. RANGE

PIN- PACK AGE

SU PPL Y

VO LT A G E

( V)

MAX5258EEE

-40

C to +85

16 QSOP +5.0

MAX5259EEE

-40

C to +85

16 QSOP +3.0

SPI and QSPI are trademarks of Motorola, Inc.

MICROWIRE is a trademark of National Semiconductor Corp.

MAX5258/MAX5259

Rail-to-Rail is a registered trademark of Nippon Motorola, Ltd.

For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,

or visit Maxim’s website at www.maxim-ic.com.

Summary of content (20 pages)

PAGE 1
9-1844; Rev 1; 4/01 KIT ATION EVALU E L B A IL AVA +3V/+5V, Low-Power, 8-Bit Octal DACs with Rail-to-Rail Output Buffers Features The MAX5258/MAX5259 are +3V/+5V single-supply, digital serial-input, voltage-output, 8-bit octal digital-toanalog converters (DACs). Internal precision buffers swing Rail-to-Rail ® , and the reference input range extends from ground to the positive supply. The +5V (MAX5258) and the +3V (MAX5259) feature a 10µA (max) shutdown mode. The serial interface is double-buffered.
PAGE 2
MAX5258/MAX5259 +3V/+5V, Low-Power, 8-Bit Octal DAC with Rail-to-Rail Output Buffers ABSOLUTE MAXIMUM RATINGS VDD to GND ..............................................................-0.3V to +6V DIN, DOUT, CS, SCLK, LDAC to GND.....................-0.3V to +6V REF to GND ................................................-0.3V to (VDD + 0.3V) OUT_ to GND ...........................................................-0.3V to VDD Maximum Current into Any Pin............................................
PAGE 3
+3V/+5V, Low-Power, 8-Bit Octal DAC with Rail-to-Rail Output Buffers (VDD = +4.5V to +5.5V, VREF = +4.096V, GND = 0, RL = 10kΩ, CL = 100pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at VDD = +5V and TA = +25°C.) PARAMETER SYMBOL CONDITIONS Input Current IIN VIN = 0 to VDD Input Capacitance CIN (Note 3) Output High Voltage VOH ISOURCE = 0.2mA Output Low Voltage VOL ISINK = 1.6mA MIN TYP MAX UNITS ±1.0 µA 10 pF DIGITAL OUTPUTS VDD 0.5 V 0.
PAGE 4
MAX5258/MAX5259 +3V/+5V, Low-Power, 8-Bit Octal DAC with Rail-to-Rail Output Buffers ELECTRICAL CHARACTERISTICS (MAX5259) (VDD = +2.7V to +3.3V, VREF = +2.5V, GND = 0, RL = 10kΩ, CL = 100pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at VDD = +3V, and TA = +25°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS ±0.1 ±1 LSB STATIC ACCURACY Resolution 8 Bits Integral Non Linearity (Note 1) INL Differential Non Linearity (Note 1) DNL Guaranteed monotonic (all codes) ±0.
PAGE 5
+3V/+5V, Low-Power, 8-Bit Octal DAC with Rail-to-Rail Output Buffers (VDD = +2.7V to +3.3V, VREF = +2.5V, GND = 0, RL = 10kΩ, CL = 100pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at VDD = +3V, and TA = +25°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Digital Feedthrough Code = 00 hex 0.1 nV-s Digital-to-Analog Glitch Impulse Code = 80 to code = 7F hex 20 nV-S VREF = 2.5Vp-p at 1kHz centered at 1.
PAGE 6
MAX5258/MAX5259 +3V/+5V, Low-Power, 8-Bit Octal DAC with Rail-to-Rail Output Buffers TIMING CHARACTERISTICS (MAX5259) (VREF = +2.5V, GND = 0, CDOUT = 100pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at VDD = +3V and TA = +25°C.
PAGE 7
+3V/+5V, Low-Power, 8-Bit Octal DAC with Rail-to-Rail Output Buffers 500 400 300 200 100 0 1.25 1.00 0.75 0.50 0.25 0 2 3 4 5 1 DAC OUTPUT SINK CURRENT (mA) 2 3 4 5 6 7 1.6 MAX5258/9 toc04 4.5 4.0 3.5 3.0 ALL DAC CODES = FF HEX 1.4 SUPPLY CURRENT (mA) 5.0 2.0 5 6 7 0.8 8 2 3 4 5 6 7 1.6 ALL DAC CODES = OO HEX VDD = +3.0V VREF = +2.5V ALL DAC CODES = FF HEX 1.4 1.2 1.0 ALL DAC CODES = OO HEX 0.8 VDD = +5.0V VREF = +4.5V 0.6 0.
PAGE 8
Typical Operating Characteristics (continued) (TA = +25°C, unless otherwise noted.) THD + NOISE AT DAC OUTPUT vs. REFERENCE AMPLITUDE -10 -20 THD + NOISE (dB) ALL DAC CODES = FF HEX 1.2 1.0 0.8 ALL DAC CODES = OO HEX 0.6 -30 -40 VREF = 20kHz -50 VREF = 1kHz -70 0.2 -80 0 1 2 3 4 5 -40 -45 VREF = 0.5Vp-p -50 0 0.5 1.0 1.5 2.0 -60 VREF = 1Vp-p -65 VREF = 2Vp-p -70 10 100 1k 100k REFERENCE INPUT FREQUENCY RESPONSE REFERENCE FEEDTHROUGH vs.
PAGE 9
+3V/+5V, Low-Power, 8-Bit Octal DAC with Rail-to-Rail Output Buffers WORST-CASE 1LSB DIGITAL STEP CHANGE (NEGATIVE) CLOCK FEEDTHROUGH MAX5258/9 toc19 MAX5258/9 toc18 3V 3V SCLK CS 0 0 OUTA 50mV/div VDD = +5V VREF = +4.5V 1mV/div OUTA 1µs/div DAC CODE = 00 HEX VDD = +3V VREF = +2.5V NO-LOAD SCLK = 333 kHz 1µs/div DAC CODE = 80 TO 7F HEX NO-LOAD POSITIVE SETTLING TIME POSITIVE SETTLING TIME MAX5258/9 toc21 MAX5258/9 toc20 3V 3V CS CS 0 0 2.0V/div 1.
PAGE 10
+3V/+5V, Low-Power, 8-Bit Octal DAC with Rail-to-Rail Output Buffers MAX5258/MAX5259 Pin Description PIN 1 NAME OUTB FUNCTION 2 OUTA DAC A Voltage Output 3 GND Ground 4 VDD Power Supply 5 REF DAC B Voltage Output Reference Voltage Input Load DAC Input. Driving this asynchronous input low transfers the contents of each input register to its respective DAC registers.
PAGE 11
+3V/+5V, Low-Power, 8-Bit Octal DAC with Rail-to-Rail Output Buffers MAX5258/MAX5259 INSTRUCTION EXECUTED CS SCLK DIN X X A2 A1 A0 C2 C1 C0 D7 D6 D5 D4 D3 D2 D1 D0 X X A2 A1 A0 C2 C1 C0 D7 D6 D5 D4 D3 D2 D1 D0 DACA DACA X X A2 A1 A0 C2 C1 C0 D7 D6 D5 D4 D3 D2 D1 D0 X X A2 A1 A0 C2 C1 C0 D7 D6 D5 D4 D3 D2 D1 D0 DOUT MODE 1 DATA FROM PREVIOUS DATA INPUT DATA FROM PREVIOUS DATA INPUT X X A2 A1 A0 C2 C1 C0 D7 D6 D5 D4 D3 D2 D1 D0 X X A2 A1 A0 C2 C1 C0 D7 D6 D5 D4 D3 D2 D1 D0 DOUT MODE 0 (DEFAULT)
PAGE 12
MAX5258/MAX5259 +3V/+5V, Low-Power, 8-Bit Octal DAC with Rail-to-Rail Output Buffers Table 1. Serial-Interface Programming Commands LDAC 16-BIT SERIAL WORD* A2 A1 A0 C2 C1 C0 D7……D0 X X X 0 0 0 XXXXXXXX FUNCTION X No operation (NOP); shift data in shift registers. X X X 0 0 1 XXXXXXXX X Clears all input and DAC registers and sets all DAC outputs to zero. X X X 0 1 0 XXXXXXXX X Software shutdown.
PAGE 13
+3V/+5V, Low-Power, 8-Bit Octal DAC with Rail-to-Rail Output Buffers A2 A1 Don’t Care A0 C2 0 C1 0 C0 0 D7 D6 D5 D4 D3 Don’t Care D2 D1 D0 (LDAC = X) The no-operation (NOP) command allows data to be shifted through the MAX5258/MAX5259 shift register without affecting the input or DAC registers. This is useful in daisy-chaining (see the Daisy-Chaining Devices section). For this command, the data bits are "Don’t Cares.
PAGE 14
MAX5258/MAX5259 +3V/+5V, Low-Power, 8-Bit Octal DAC with Rail-to-Rail Output Buffers Load All DACs with Shift-Register Data A2 A1 Don’t Care A0 C2 1 C1 0 C0 0 D7 D6 D5 D4 D3 8-Bit Data D2 D1 D0 (LDAC = X) All eight DAC registers are updated with shift-register data. This command allows all DACs to be set to any analog value within the reference range. This command can be used to substitute CLEAR if code 00 (hex) is programmed, which clears all DACs.
PAGE 15
+3V/+5V, Low-Power, 8-Bit Octal DAC with Rail-to-Rail Output Buffers Serial Data Output DOUT is the internal shift-register’s output. DOUT can be programmed to clock out data on the falling edge of SCLK (mode 0) or the rising edge (mode 1). In mode 0, output data lags input data by 16.5 clock cycles, maintaining compatibility with MICROWIRE and SPI. In mode 1, output data lags input data by 16 clock cycles. On power-up, DOUT defaults to mode 0 timing.
PAGE 16
MAX5258/MAX5259 +3V/+5V, Low-Power, 8-Bit Octal DAC with Rail-to-Rail Output Buffers DIN SCLK LDAC CS1 TO OTHER SERIAL DEVICES CS2 CS3 CS CS CS MAX5258/ LDAC MAX5259 MAX5258/ LDAC MAX5259 LDAC MAX5259 SCLK SCLK SCLK DIN DIN DIN MAX5258/ Figure 4. Multiple MAX5258’s Sharing One DIN Line.
PAGE 17
+3V/+5V, Low-Power, 8-Bit Octal DAC with Rail-to-Rail Output Buffers MAX5258/MAX5259 REF R0 R1 R15 D7 D5 R16 MSB DECODER D6 OUTPUT VOLTAGE D4 R255 O NEGATIVE OFFSET DAC CODE LSB DECODER D3 D2 D1 D0 DAC A Figure 8. DAC Simplified Circuit Diagram Figure 9. Effect of Negative Offset (Single Supply) ratings. Do not apply signals to the digital inputs before the device is fully powered-up.
PAGE 18
MAX5258/MAX5259 +3V/+5V, Low-Power, 8-Bit Octal DAC with Rail-to-Rail Output Buffers REFERENCE INPUT REF Table 2.
PAGE 19
+3V/+5V, Low-Power, 8-Bit Octal DAC with Rail-to-Rail Output Buffers DOUT VDD LDAC REF DECODE CONTROL OUT A INPUT REGISTER A DAC REGISTER A INPUT REGISTER B DAC REGISTER B INPUT REGISTER C DAC REGISTER C INPUT REGISTER D DAC REGISTER D INPUT REGISTER E DAC REGISTER E INPUT REGISTER F DAC REGISTER F INPUT REGISTER G DAC REGISTER G INPUT REGISTER H DAC REGISTER H DAC A OUT B DAC B OUT C DAC C OUT D 16-BIT SHIFT REGISTER DAC D OUT E DAC E OUT F DAC F OUT G DAC G OUT H SR CONTROL
PAGE 20
Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.) QSOP.EPS MAX5258/MAX5259 +3V/+5V, Low-Power, 8-Bit Octal DAC +5V/+3V, with Rail-to-Rail Output Buffers Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied.