Datasheet

sequence is initiated on a falling edge of CS. If CS

goes high prior to completing 16 cycles of SCLK, the

input data is discarded. To initiate a new data transfer,

drive CS low again. The serial clock (SCLK) can be

either high or low between CS write pulses. Figure 4

shows the timing diagram for the complete 3-wire serial

interface transmission.

The MAX5306/MAX5307 digital inputs are double-

buffered. Depending on the command issued through

the serial interface, the input register(s) can be loaded

without affecting the DAC register(s), the DAC regis-

ter(s) can be loaded directly, or all eight registers can

be updated simultaneously from the input registers.

Shutdown Modes

The MAX5306/MAX5307 include three software-con-

trolled shutdown modes that reduce the supply current

to less than 1µA. In two of the three shutdown modes

(shutdown 2 and 3) the outputs are independently con-

MAX5306/MAX5307

Low-Power, Low-Glitch, Octal 12-Bit Voltage-

Output DACs with Serial Interface

_______________________________________________________________________________________ 9

INPUT

DAC

OUT1

OUT2

OUT3

OUT4

OUT5

OUT6

OUT7

OUT8

SCLK

DIN

(MAX5307) CLR

REF

LDAC

(MAX5306) DOUT

INPUT

DAC

SERIAL TO PARALLEL

SHIFT REGISTER

MAX5306

MAX5307

GND

Figure 1. Functional Block Diagram