Datasheet

MAX530
+5V, Low-Power, Parallel-Input,
Voltage-Output, 12-Bit DAC
12 ______________________________________________________________________________________
A0 = 1, A1 = 1
NBH
NBM
NBL
CS
WR
LDAC
A0 = 1, A1 = 0
A0 = 0, A1 = 1
DAC UPDATE
Figure 6. 4-Bit µP Timing Sequence
A0 = A1 = 1
A0 = A1 = 0
DAC UPDATE
NBH
NBL & NBM
CS
WR
LDAC
Figure 8a. 8-Bit and 16-Bit µP Timing Sequence Using LDAC
Figure 5. 4-Bit µP Interface
DATA BUS
D0-D3 D0-D3
D0-D3
D4-D7
MC6800
FROM
SYSTEM
RESET

02
R/W
CLR
WR CS
LDAC
EN
DECODER
A0-A15
A13-A15
ADDRESS BUS A0, A1
A0, A1
D0-D3
MAX530
Figure 7. 8-Bit and 16-Bit µP Interface
D0-D7
DATA BUS
D0-D7
D0-D7
MC6809
FROM
SYSTEM
RESET
CLR
A0-A1
WR
CS LDAC
E
R/W
A0-A15
A13-A15
A0
ADDRESS BUS
EN
DECODER
MAX530