Datasheet
MAX5318 Evaluation System
Evaluates: MAX5318
6Maxim Integrated
Detailed Description of Software
The main window of the evaluation software (shown in
Figure 1) displays the MAXUSB2XILINXMB DDS signal
generator on the left side of the window, and the MAX5318
DAC on the right side.
When DAC Data Source is set to DDS, the MAX5318 DIN
register is driven by the DDS signal generator. The output
frequency is controlled by the Frequency track bar, or by
typing the output frequency value into its edit field and
pressing enter. The sample update rate is controlled by
the Update Frequency drop-down box.
The DDS output waveform frequency is calculated
as follows:
UPDATE INC
24
f xP
OUT
f
2
=
Where f
UPDATE
is the DDS update frequency, P
INC
is the
DDS phase increment. The DDS is implemented with a
24-bit phase accumulator.
The gain and offset of the DDS output waveform can be
adjusted by the Gain and Offset track bars in the DDS
section of the GUI.
The shape of the waveform is selected by the Waveform
group box. The SPI clock frequency is selectable under the
Advanced menu. Selecting a slower SPI clock frequency
may limit the available update frequency. If the
IC’s
GAIN
and OFFSET registers are changed, the software briefly
disables the DDS while performing the requested write
operations, then automatically re-enables the DDS.
When DAC Data Source is set to SPI/Direct, the IC’s
DIN register is driven by the controls on the right side
of the window. Write the DIN, GAIN, or OFFSET register
by dragging its track bar, or by typing numbers into the
corresponding edit fields.
When the MAXUSB2XILINXMB is powered up and
connected to the computer’s USB port, the software
automatically connects and configures the IC to enable
data output. This can be prevented by unchecking the
Advanced menu item’s
Connect Automatically and
Enable DOUT After Connecting.
Arbitrary Waveform Generation
The DDS can accept user-defined arbitrary waveform data
stored in a comma-separated values (CSV) file. There
are 1,048,576 samples stored in the file, representing
one cycle of the arbitrary waveform. The sample data are
18-bit decimal values with 0 representing zero scale and
262,143 representing full scale. Click the File menu item
Load Arbitrary Waveform… to download the waveform to
the DDS and stream to the DAC.
A staircase waveform is stored in the system at power-up.
Detailed Description of Hardware
The MAX5318 EV kit can operate in two modes: stand-
alone and GUI.
The stand-alone mode is for quick IC functional-
ity demonstration purposes only. In this mode, the
MAXUSB2XILINXMB interface board generates one of
16 predefined digital signals using the DDS implemented
on the FPGA.
Press and release SW3 to select between eight sine wave-
forms with different frequencies. A single LED from LED4–
LED11 is turned on, indicating a different frequency, as
shown in Table 1.
Press and release SW4 to select between eight sine wave-
forms with different frequencies. A single LED from LED4–
LED11 is turned off, indicating a different frequency, as
shown in Table 2.
In the stand-alone mode, the DAC is updated at 200kHz,
the SPI clock speed is set at 10MHz.
The GUI mode is for a complete feature exercise of
the IC through a PC. The user can explore many
different application cases (e.g., DAC update frequencies,
DAC output waveforms, DAC register settings, and DAC
interface speed selections, etc).
The EV kit provides a proven layout for the 18-bit high-
precision voltage output DAC. An on-board +4.096V volt-
age reference (MAX6126) is provided. Contact Maxim for
other high-precision voltage references if reference volt-
ages other than +4.096V are required.
SYNC_IN and SYNC_OUT Signals
There is an SMA connector (J5) labeled INPUT and
another SMA connector (J4) labeled OUTPUT on the
MAXUSB2XILINXMB interface board. The INPUT signal is
called SYNC_IN and the OUTPUT signal is called SYNC_
OUT, respectively.
The SYNC_IN signal is applied to the Schmitt-trigger input
and the Schmitt-trigger output is applied to the FPGA
DDS module. The SYNC_IN is used to implement a simple
“crash lock” for the DDS signal generator. At the rising
edge of the SYNC_IN clock, the DDS resets itself and the
DDS phase accumulator is reset to the POFF value written
by the GUI (default to 0).
The SYNC_OUT signal shows when the generated wave-
form starts a new cycle.
Set the SYNC_In_Out_Width register bit 31 to 1 to enable
the SYNC_IN signal. Set the bit to 0 to disable the SYNC_
IN signal.
Set the SYNC_In_Out_Width register bit 30 to 1 to enable
the SYNC_OUT signal. Set the bit to 0 to disable the
SYNC_OUT signal.