Datasheet

JUMPER
SHUNT
POSITION
DESCRIPTION
JU1
1-2
IOVDD = 1.8V from U9.
Do not use.
1-3* IOVDD = 3.3V from U7.
1-4
IOVDD = external user-
supplied IOVDD from test point
TPEXTIOVDD.
Do not use.
JU2
Pin 1 only* FPGA mode signal M0 = 1.
1-2
FPGA mode signal M0 = 0.
Do not use.
JU3
Pin 1 only
FPGA mode signal M1 = 1.
Do not use.
1-2* FPGA mode signal M1 = 0.
JU4
Pin 1 only
FPGA mode signal M2 = 1.
Do not use.
1-2* FPGA mode signal M2 = 0.
JU5
Pin 1 only* FPGA VS2 = 1.
1-2
FPGA VS2 = 0.
Do not use.
JU6
Pin 1 only* FPGA VS1 = 1.
1-2
FPGA VS1 = 0.
Do not use.
JU7
Pin 1 only* FPGA VS0 = 1.
1-2
FPGA VS0 = 0.
Do not use.
JU8
1-2*
HOLD1 is connected to ground.
2-3
HOLD2 is connected to ground.
JUMPER
SHUNT
POSITION
DESCRIPTION
JU9
1-2* U7 powers the 3.3V supply rail.
Open
Measure the MAXUSB2XILINXMB
3.3V supply current by putting a
current meter in series with the
jumper.
JU10
1-2* U8 powers the 0.9V supply rail.
Open
Measure the MAXUSB2XILINXMB
0.9V supply current by putting a
current meter in series with the
jumper.
JU11
1-2* U10 powers the 1.2V supply rail.
Open
Measure the MAXUSB2XILINXMB
1.2V supply current by putting a
current meter in series with the
jumper.
JU12
1-2* U9 powers the 1.8V supply rail.
Open
Measure the MAXUSB2XILINXMB
1.8V supply current by putting a
current meter in series with the
jumper.
JU13
1-2*
Power U7–U10 from external
user-supplied +5V DC supply
(from test point TP1).
2-3
Power U7–U10 from USB (for
FPGA configurations with
sufficiently low power).
Do not use.
MAX5318 Evaluation System
Evaluates: MAX5318
7Maxim Integrated
Table 3. MAXUSB2XILINXMB Interface Board Jumper Descriptions (JU1–JU13)
*Default position.
Set the SYNC_In_Out_Width register bit 29 to bit 0 to con-
trol the SYNC_OUT pulse width:
SYNC_OUT pulse width = SYNC_In_Out_Width[29:0] x
10ns
When SYNC_In_Out_Width[29:0] = 0, the SYNC_OUT
pulse width = 10ns.
Pushbuttons on the
MAXUSB2XILINXMB Interface Board
There are five pushbuttons (SW1–SW5) on the
MAXUSB2XILINXMB interface board. Their functions are
described as follows:
FPGA Reconfigure Button (SW1): Press and release this
button to reconfigure the FPGA and the whole interface
board.
CPU Reset Button (SW2): Press and release this button
to reset the embedded MicroBlaze microcontroller and the
interface board.
Sinusoid Frequency-Select Button (SW3): Press and
release this button to select between eight sine waveforms
with different frequencies. A single LED from LED4–LED11
is turned on, indicating a different frequency, as shown in
Table 1.
Sinusoid Frequency-Select Button (SW4): Press and
release this button to select between eight sine waveforms
with different frequencies. A single LED from LED4–LED11
is turned off, indicating a different frequency, as shown in
Table 2.
TC/SB IC Pin Logic-Level Select Button (SW5): Press
and release this button to toggle the TC/SB IC pin
logic. After the FPGA reconfiguration or the embedded
MicroBlaze microcontroller reset, the TC/SB pin is logic-
high and the DDS output is set to two’s-complement
format. If TC/SB = low, the sine waveform is distorted.