EVALUATION KIT AVAILABLE MAX5318 18-Bit, High-Accuracy Voltage Output DAC with Digital Gain, Offset Control, and SPI Interface General Description The MAX5318 is a high-accuracy, 18-bit, serial SPI input, buffered voltage output digital-to-analog converter (DAC) in a 4.4mm x 7.8mm, 24-lead TSSOP package. The device features Q2 LSB INL (max) accuracy and a Q1 LSB DNL (max) accuracy over the full temperature range of -40NC to +105NC.
MAX5318 18-Bit, High-Accuracy Voltage Output DAC with Digital Gain, Offset Control, and SPI Interface ABSOLUTE MAXIMUM RATINGS AGND to DGND....................................................-0.3V to +0.3V AGND_F, AGND_S to AGND................................-0.3V to +0.3V AGND_F, AGND_S to DGND................................-0.3V to +0.3V AVDD to AGND........................................................-0.3V to +6V AVDD to REF............................................................-0.
MAX5318 18-Bit, High-Accuracy Voltage Output DAC with Digital Gain, Offset Control, and SPI Interface ELECTRICAL CHARACTERISTICS (continued) (VAVDD = VDDIO = 4.5V to 5.5V, VAVSS = -1.25V, VAGND = VDGND = VAGND_F = VAGND_S = 0V, VREF = 4.096V, TC/SB = PD = LDAC = M/Z = DGND, RST = VDDIO, CREFO = 100pF, CL = 100pF, RL = 10kω, CBYPASS = 1µF, TA = -40°C to +105°C, unless otherwise noted. Typical values are at TA = +25°C.) (GAIN = 0x3FFFF and OFFSET = 0x00000.
MAX5318 18-Bit, High-Accuracy Voltage Output DAC with Digital Gain, Offset Control, and SPI Interface ELECTRICAL CHARACTERISTICS (continued) (VAVDD = VDDIO = 4.5V to 5.5V, VAVSS = -1.25V, VAGND = VDGND = VAGND_F = VAGND_S = 0V, VREF = 4.096V, TC/SB = PD = LDAC = M/Z = DGND, RST = VDDIO, CREFO = 100pF, CL = 100pF, RL = 10kω, CBYPASS = 1µF, TA = -40°C to +105°C, unless otherwise noted. Typical values are at TA = +25°C.) (GAIN = 0x3FFFF and OFFSET = 0x00000.
MAX5318 18-Bit, High-Accuracy Voltage Output DAC with Digital Gain, Offset Control, and SPI Interface ELECTRICAL CHARACTERISTICS (VAVDD = VDDIO = 2.7V to 3.3V, VAVSS = -1.25V, VAGND = VDGND = VAGND_F = VAGND_S = 0V, VREF = 2.5V, TC/SB = PD = LDAC = M/Z = DGND, RST = VDDIO, CREFO = 100pF, CL = 100pF, RL = 10kω, CBYPASS = 1µF, GAIN = 0x3FFFF, OFFSET = 0x00000, TA = -40°C to +105°C, unless otherwise noted. Typical values are at TA = +25°C.) (GAIN = 0x3FFFF and OFFSET = 0x00000.
MAX5318 18-Bit, High-Accuracy Voltage Output DAC with Digital Gain, Offset Control, and SPI Interface ELECTRICAL CHARACTERISTICS (continued) (VAVDD = VDDIO = 2.7V to 3.3V, VAVSS = -1.25V, VAGND = VDGND = VAGND_F = VAGND_S = 0V, VREF = 2.5V, TC/SB = PD = LDAC = M/Z = DGND, RST = VDDIO, CREFO = 100pF, CL = 100pF, RL = 10kω, CBYPASS = 1µF, GAIN = 0x3FFFF, OFFSET = 0x00000, TA = -40°C to +105°C, unless otherwise noted. Typical values are at TA = +25°C.) (GAIN = 0x3FFFF and OFFSET = 0x00000.
MAX5318 18-Bit, High-Accuracy Voltage Output DAC with Digital Gain, Offset Control, and SPI Interface ELECTRICAL CHARACTERISTICS (continued) (VAVDD = VDDIO = 2.7V to 3.3V, VAVSS = -1.25V, VAGND = VDGND = VAGND_F = VAGND_S = 0V, VREF = 2.5V, TC/SB = PD = LDAC = M/Z = DGND, RST = VDDIO, CREFO = 100pF, CL = 100pF, RL = 10kω, CBYPASS = 1µF, GAIN = 0x3FFFF, OFFSET = 0x00000, TA = -40°C to +105°C, unless otherwise noted. Typical values are at TA = +25°C.) (GAIN = 0x3FFFF and OFFSET = 0x00000.
MAX5318 18-Bit, High-Accuracy Voltage Output DAC with Digital Gain, Offset Control, and SPI Interface DIGITAL INTERFACE ELECTRICAL CHARACTERISTICS (continued) (VAVDD = 5V, VDDIO = 2.7V to 5.5V, VAVSS = -1.25V, VREF = 4.096V, RL = 10kω, TC/SB = M/Z = DGND, CREFO = 100pF, CBYPASS = 1µF, TA = -40°C to +105°C, unless otherwise noted. Typical values are at TA = +25°C.)(GAIN = 0x3FFFF and OFFSET = 0x00000.
MAX5318 18-Bit, High-Accuracy Voltage Output DAC with Digital Gain, Offset Control, and SPI Interface DIGITAL INTERFACE ELECTRICAL CHARACTERISTICS (VAVDD = 5V, VDDIO = 1.8V to 2.7V, VAVSS = -1.25V, VREF = 4.096V, RL = 10kω, TC/SB = M/Z = DGND, CREFO = 100pF, CBYPASS = 1µF, TA = -40°C to +105°C, unless otherwise noted. Typical values are at TA = +25°C.)(GAIN = 0x3FFFF and OFFSET = 0x00000.
MAX5318 18-Bit, High-Accuracy Voltage Output DAC with Digital Gain, Offset Control, and SPI Interface DIGITAL INTERFACE ELECTRICAL CHARACTERISTICS (continued) (VAVDD = 5V, VDDIO = 1.8V to 2.7V, VAVSS = -1.25V, VREF = 4.096V, RL = 10kω, TC/SB = M/Z = DGND, CREFO = 100pF, CBYPASS = 1µF, TA = -40°C to +105°C, unless otherwise noted. Typical values are at TA = +25°C.)(GAIN = 0x3FFFF and OFFSET = 0x00000.
MAX5318 18-Bit, High-Accuracy Voltage Output DAC with Digital Gain, Offset Control, and SPI Interface Typical Operating Characteristics (VAVDD = VDDIO = 5V, VAVSS = -1.25V, VAGND = VDGND = VAGND_F = VAGND_S = 0V; VREF = 4.096V, TC/SB = PD = M/Z = DGND, RST = VDDIO, CREFO = 100pF, CL = 100pF, RL = 10kω, CBYPASS = 1µF, TA = +25°C, unless otherwise noted.) 1.2 1.2 0.4 -0.4 INL (LSB) 0.4 INL (LSB) 0.8 0.4 0 0 -0.4 0 -0.4 -0.8 -0.8 -0.8 -1.2 -1.2 -1.2 -1.6 -1.6 -1.6 -2.0 -2.
MAX5318 18-Bit, High-Accuracy Voltage Output DAC with Digital Gain, Offset Control, and SPI Interface Typical Operating Characteristics (continued) (VAVDD = VDDIO = 5V, VAVSS = -1.25V, VAGND = VDGND = VAGND_F = VAGND_S = 0V; VREF = 4.096V, TC/SB = PD = M/Z = DGND, RST = VDDIO, CREFO = 100pF, CL = 100pF, RL = 10kω, CBYPASS = 1µF, TA = +25°C, unless otherwise noted.) -0.4 0 -0.8 -1.6 -3.2 -2.0 -4.0 -40 -25 -10 5 20 35 50 65 80 95 110 INTEGRAL NONLINEARITY vs. TEMPERATURE 100 +25°C 1.6 +105°C 0.
MAX5318 18-Bit, High-Accuracy Voltage Output DAC with Digital Gain, Offset Control, and SPI Interface Typical Operating Characteristics (continued) (VAVDD = VDDIO = 5V, VAVSS = -1.25V, VAGND = VDGND = VAGND_F = VAGND_S = 0V; VREF = 4.096V, TC/SB = PD = M/Z = DGND, RST = VDDIO, CREFO = 100pF, CL = 100pF, RL = 10kω, CBYPASS = 1µF, TA = +25°C, unless otherwise noted.) DIFFERENTIAL NONLINEARITY vs. SUPPLY VOLTAGE MAX DNL 0.8 0.8 +105°C 0.4 0.4 30 -0.4 -0.8 20 MIN DNL -2.0 2.7 3.1 3.5 3.9 4.3 4.
MAX5318 18-Bit, High-Accuracy Voltage Output DAC with Digital Gain, Offset Control, and SPI Interface Typical Operating Characteristics (continued) (VAVDD = VDDIO = 5V, VAVSS = -1.25V, VAGND = VDGND = VAGND_F = VAGND_S = 0V; VREF = 4.096V, TC/SB = PD = M/Z = DGND, RST = VDDIO, CREFO = 100pF, CL = 100pF, RL = 10kω, CBYPASS = 1µF, TA = +25°C, unless otherwise noted.) 0 -0.4 -0.8 1 SINKING 0 SOURCING -1 -2 -1.2 -3 -1.6 -2.0 3.1 3.5 3.9 4.3 4.7 5.1 -4 5.
MAX5318 18-Bit, High-Accuracy Voltage Output DAC with Digital Gain, Offset Control, and SPI Interface Typical Operating Characteristics (continued) (VAVDD = VDDIO = 5V, VAVSS = -1.25V, VAGND = VDGND = VAGND_F = VAGND_S = 0V; VREF = 4.096V, TC/SB = PD = M/Z = DGND, RST = VDDIO, CREFO = 100pF, CL = 100pF, RL = 10kω, CBYPASS = 1µF, TA = +25°C, unless otherwise noted.) +105°C SINKING 0 SOURCING -1 -2 -3 40 30 10 10 6 9 12 15 18 21 24 27 30 0 -2.0 -1.8 -1.6 -1.4 -1.2 -1.0 -0.8 -0.6 -0.4 -0.2 0 -2.
MAX5318 18-Bit, High-Accuracy Voltage Output DAC with Digital Gain, Offset Control, and SPI Interface Typical Operating Characteristics (continued) (VAVDD = VDDIO = 5V, VAVSS = -1.25V, VAGND = VDGND = VAGND_F = VAGND_S = 0V; VREF = 4.096V, TC/SB = PD = M/Z = DGND, RST = VDDIO, CREFO = 100pF, CL = 100pF, RL = 10kω, CBYPASS = 1µF, TA = +25°C, unless otherwise noted.) OUTPUT DRIVE CAPABILITY 0 -2 -4 4 2 0 -2 -6 -8 -8 -10 -10 5 CODE = 0x00000 VAVSS = -1.25V VREF = 2.
MAX5318 18-Bit, High-Accuracy Voltage Output DAC with Digital Gain, Offset Control, and SPI Interface Typical Operating Characteristics (continued) (VAVDD = VDDIO = 5V, VAVSS = -1.25V, VAGND = VDGND = VAGND_F = VAGND_S = 0V; VREF = 4.096V, TC/SB = PD = M/Z = DGND, RST = VDDIO, CREFO = 100pF, CL = 100pF, RL = 10kω, CBYPASS = 1µF, TA = +25°C, unless otherwise noted.) MAX5318 toc27 100 CODE = 0x20000 VOUT 1µV/div VOLTAGE NOISE (nV/rt-Hz) 90 80 MAX5318 toc28 OUTPUT NOISE DENSITY 0.
MAX5318 18-Bit, High-Accuracy Voltage Output DAC with Digital Gain, Offset Control, and SPI Interface Typical Operating Characteristics (continued) (VAVDD = VDDIO = 5V, VAVSS = -1.25V, VAGND = VDGND = VAGND_F = VAGND_S = 0V; VREF = 4.096V, TC/SB = PD = M/Z = DGND, RST = VDDIO, CREFO = 100pF, CL = 100pF, RL = 10kω, CBYPASS = 1µF, TA = +25°C, unless otherwise noted.
MAX5318 18-Bit, High-Accuracy Voltage Output DAC with Digital Gain, Offset Control, and SPI Interface Typical Operating Characteristics (continued) (VAVDD = VDDIO = 5V, VAVSS = -1.25V, VAGND = VDGND = VAGND_F = VAGND_S = 0V; VREF = 4.096V, TC/SB = PD = M/Z = DGND, RST = VDDIO, CREFO = 100pF, CL = 100pF, RL = 10kω, CBYPASS = 1µF, TA = +25°C, unless otherwise noted.
MAX5318 18-Bit, High-Accuracy Voltage Output DAC with Digital Gain, Offset Control, and SPI Interface Pin Configuration TOP VIEW RST 1 READY + 24 VDDIO 2 23 DGND M/Z 3 22 BYPASS BUSY 4 21 AVDD2 LDAC 5 20 AGND_F DOUT 6 19 AGND_S DIN 7 18 REF SCLK 8 17 REFO CS 9 16 RFB TC/SB 10 15 OUT PD 11 14 AVDD1 AVSS 12 13 AGND MAX5318 TSSOP Pin Description PIN NAME FUNCTION 1 RST Active-Low Reset Input. Drive RST low to DGND to put the device into a reset state.
MAX5318 18-Bit, High-Accuracy Voltage Output DAC with Digital Gain, Offset Control, and SPI Interface Pin Description (continued) PIN NAME FUNCTION 5 LDAC Active-Low Load DAC Logic Input. If LDAC is taken low while BUSY is inactive (high), the contents of the input registers are transferred to the DAC register and the DAC output is updated. If LDAC is taken low while BUSY is asserted low, the LDAC event is stored and the DAC register update is delayed until BUSY deasserts.
MAX5318 18-Bit, High-Accuracy Voltage Output DAC with Digital Gain, Offset Control, and SPI Interface Detailed Description up before AVDD at power up. Follow the recommendations described in the Power-Supply Sequencing section. The MAX5318 is a high-accuracy, 18-bit, serial SPI input, buffered voltage output digital-to-analog converter (DAC) in a 4.4mm x 7.8mm, 24-lead TSSOP package.
MAX5318 18-Bit, High-Accuracy Voltage Output DAC with Digital Gain, Offset Control, and SPI Interface 18-Bit Ideal Transfer Function The MAX5318 features 18-bit gain and 18-bit offset adjustment as shown in Figure 3. The incoming DIN code is multiplied and offset compensated by the generic equation shown in Equation 1. The resulting value is then applied to the DAC.
MAX5318 18-Bit, High-Accuracy Voltage Output DAC with Digital Gain, Offset Control, and SPI Interface The data DIN can be either straight binary or two’s complement. In straight binary, zero code results in a zeroscale output. In two’s complement, zero code results in a midscale output. To better understand how GAIN and OFFSET affect the output voltage, see Figure 4 and Figure 5. Consider the generation of a ramp. For now assume OFFSET is set to 0x00000.
MAX5318 18-Bit, High-Accuracy Voltage Output DAC with Digital Gain, Offset Control, and SPI Interface Conversion Formulas for DIN, GAIN, and OFFSET Input, Gain, and Offset Ranges The ranges of DIN, GAIN, and OFFSET are summarized in Table 4 to Table 6. Also shown are the range values for the 18-bit MAX5318 with a 4.096V reference. Note that VREF is the reference voltage applied to REF and 1 LSB is equal to VREF/218.
MAX5318 18-Bit, High-Accuracy Voltage Output DAC with Digital Gain, Offset Control, and SPI Interface Table 4a. DIN Range (Straight Binary Mode) RANGE DIN VDIN (V) VALUE (V) Minimum 0x00000 0 0 Maximum 0x3FFFF (VREF - 1 LSB) 4.095984375 Table 4b. DIN Range (Two’s Complement Mode) RANGE DIN VDIN (V) VALUE (V) Minimum 0x20000 0 0 Maximum 0x1FFFF (VREF - 1 LSB) 4.095984375 Table 5. GAIN Range RANGE GAIN G VALUE (V) Minimum 0x00000 1/218 0.
MAX5318 18-Bit, High-Accuracy Voltage Output DAC with Digital Gain, Offset Control, and SPI Interface Table 8. Two’s Complement DIN Examples DIN 0x30000 0x10000 VDIN (V) -1.024 1.024 GAIN 0x2FFFF 0x0FFFF G 0.75 0.25 OFFSET 0x08000 0x38000 VOFFSET (V) CALCULATION 0.512 VOUT = 4.096/2 + 0.75 x (-1.024) + 0.512 = 1.792V • • • • For VOUT, use Equation 4 For VDIN, use Table 1b first formula For G, use Table 2 For VOFFSET, use Table 3 second formula -0.512 VOUT = 4.096/2 + 0.25 x 1.024 - 0.
MAX5318 18-Bit, High-Accuracy Voltage Output DAC with Digital Gain, Offset Control, and SPI Interface LDAC and BUSY Interaction event but does not implement it until processing is complete. Then, BUSY goes high and the device updates the DAC. The BUSY line is open drain and is normally pulled up by an external resistor. It is software-configurable bidirectional and can be pulled down externally.
MAX5318 18-Bit, High-Accuracy Voltage Output DAC with Digital Gain, Offset Control, and SPI Interface Serial Interface upon the type of read command. Table 9 shows the bit positions for DOUT and DIN within the 24-bit SPI frame. Overview The SPI interface supports speeds up to 50MHz. When CS is high, the remaining interface inputs are disabled to reduce transient currents. The interface supports daisy chaining to enable multiple devices to be controlled on the same SPI bus.
MAX5318 18-Bit, High-Accuracy Voltage Output DAC with Digital Gain, Offset Control, and SPI Interface µC MISO MOSI SCK SLAVE 1 SLAVE 2 CS DOUT DIN SCLK DOUT DIN SCLK DOUT DIN SCLK I/O SLAVE 3 READY READY CS READY CS Figure 7. Daisy-Chain SPI Connection Terminating with a Standard SPI Device.
MAX5318 18-Bit, High-Accuracy Voltage Output DAC with Digital Gain, Offset Control, and SPI Interface Command and Register Map All command and data registers have read and write functionality. The register selected depends on the command select bits R[3:0]. Each write to the device consists of 4 command select bits (R[3:0]), 18 data bits (which are detailed in Table 11 to Table 19), and 2 don’t care LSBs. A summary of the commands is shown in Table 10.
MAX5318 18-Bit, High-Accuracy Voltage Output DAC with Digital Gain, Offset Control, and SPI Interface Register Details Table 11. No-Op Command (0x0) BIT 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 NAME X X X X X X X X X X X X X X X X X X DEFAULT X X X X X X X X X X X X X X X X X X BIT NAME 17:0 DESCRIPTION No action on SPI shift register and DAC input registers. Use for daisy-chain purposes when R[3:0] = 0000. Don’t care Table 12a.
MAX5318 18-Bit, High-Accuracy Voltage Output DAC with Digital Gain, Offset Control, and SPI Interface Table 13. OFFSET Register Write in Two’s Complement (0x2) BIT 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 NAME B17 B16 B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 DEFAULT 0x00000—Zero Offset BIT NAME 17:0 DESCRIPTION 18-bit offset code in two’s complement format.
MAX5318 18-Bit, High-Accuracy Voltage Output DAC with Digital Gain, Offset Control, and SPI Interface Table 15. General Configuration Write Register (0x4) BIT NAME 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PD_SW NO_HOLDEN X X X X X X X X X X X X X 0 NO_BUSY 0 DOUT_ON 0 RST_SW 1 0 X X X X X X X X X X X X X DEFAULT BIT NAME 17 PD_SW DESCRIPTION Software PD (Power-Down). Equivalent to the PD input. 0: Normal mode 1: Power-down mode.
MAX5318 18-Bit, High-Accuracy Voltage Output DAC with Digital Gain, Offset Control, and SPI Interface Table 16. DIN Read Register (0x9) BIT NAME DEFAULT 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 B17 B16 B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIT NAME 17:0 B[17:0] DESCRIPTION 18-bit DIN readback value. Table 17.
MAX5318 18-Bit, High-Accuracy Voltage Output DAC with Digital Gain, Offset Control, and SPI Interface Table 19. General Configuration and Status Read Register (0xC) BIT NAME 17 16 15 14 13 12 11 10 9 8 7 6 5 2 1 0 PD_SW NO_ HOLDEN RST_SW NO_BUSY DOUT_ON BUSY X X X X X X REV_ID[3:0] X X 0 0 1 0 0 0 0 0 0 0 0001 0 0 DEFAULT BIT 17 NAME PD_SW 0 0 4 3 DESCRIPTION Software PD (Power-Down). Equivalent to the PD input. 0: Normal mode. 1: Power-down mode.
MAX5318 18-Bit, High-Accuracy Voltage Output DAC with Digital Gain, Offset Control, and SPI Interface Power Supplies and Bypassing Considerations For best performance, use a separate supply for the MAX5318. Bypass VDDIO, AVDD_, and AVSS with highquality ceramic capacitors to a low-impedance ground as close as possible to the device. A typical high-quality X5R 10FF capacitor can become self resonant at 2MHz. Therefore, it is actually an inductor above 2MHz and is useless for decoupling signals above 2MHz.
MAX5318 18-Bit, High-Accuracy Voltage Output DAC with Digital Gain, Offset Control, and SPI Interface Voltage Reference Selection and Layout The voltage reference should be placed close to the DAC. The same power-supply decoupling and grounding rules as the DAC should be implemented. Many voltage references require an output capacitor for stability or noise reduction.
MAX5318 18-Bit, High-Accuracy Voltage Output DAC with Digital Gain, Offset Control, and SPI Interface Offset Error Digital Feedthrough Offset error indicates how well the actual transfer function matches the ideal transfer function at a single point. Typically, the point at which the offset error is specified is at or near the zero-scale point of the transfer function. Digital feedthrough is the amount of noise that appears on the DAC output when the DAC digital control lines are toggled.
MAX5318 18-Bit, High-Accuracy Voltage Output DAC with Digital Gain, Offset Control, and SPI Interface Typical Operating Circuit 2.4V TO (VAVDD - 0.1V) 0.1µF 2.0kI BUSY 4 M/Z 3 2.7V TO 5V MBR0530T1G 1.8V TO 5V 0.01µF 1µF 0.1µF 10µF VDDIO REF BYPASS AVDD2 AVDD1 24 18 22 21 14 0.
MAX5318 18-Bit, High-Accuracy Voltage Output DAC with Digital Gain, Offset Control, and SPI Interface Revision History REVISION NUMBER REVISION DATE 0 9/12 DESCRIPTION Initial release PAGES CHANGED — Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
