Datasheet

ManualsBrandsMAXIM INTEGRATED ManualsData collecting ICsData acquisition IC - DA converter (DAC) QSOP 16

_______________General Description

The MAX533 serial-input, voltage-output, 8-bit quad

digital-to-analog converter (DAC) operates from a sin-

gle +2.7V to +3.6V supply. Internal precision buffers

swing rail to rail, and the reference input range includes

both ground and the positive rail. The MAX533 features

a 1µA shutdown mode.

The serial interface is double buffered: a 12-bit input

shift register is followed by four 8-bit buffer registers

and four 8-bit DAC registers. The 12-bit serial word

consists of eight data bits and four control bits (for DAC

selection and special programming commands). Both

the input and DAC registers can be updated indepen-

dently or simultaneously with a single software com-

mand. Two additional asynchronous control pins, LDAC

and CLR, provide simultaneous updating or clearing of

the input and DAC registers.

The interface is compatible with SPI™, QSPI™ (CPOL =

CPHA = 0 or CPOL = CPHA = 1), and Microwire™. A

buffered data output allows daisy chaining of serial

devices.

In addition to 16-pin DIP and CERDIP packages, the

MAX533 is available in a 16-pin QSOP that occupies

the same area as an 8-pin SO.

________________________Applications

Digital Gain and Offset Adjustments

Programmable Attenuators

Programmable Current Sources

Portable Instruments

____________________________Features

♦ +2.7V to +3.6V Single-Supply Operation

♦ Ultra-Low Supply Current:

0.7mA while Operating

1µA in Shutdown Mode

♦ Ultra-Small 16-Pin QSOP Package

♦ Ground to V

Reference Input Range

♦ Output Buffer Amplifiers Swing Rail to Rail

♦ 10MHz Serial Interface, Compatible with SPI, QSPI

(CPOL = CPHA = 0 or CPOL = CPHA = 1), and

Microwire

♦ Double-Buffered Registers for Synchronous

Updating

♦ Serial Data Output for Daisy Chaining

♦ Power-On Reset Clears Serial Interface and Sets

All Registers to Zero

♦ Software Shutdown

♦ Software-Programmable Logic Output

♦ Asynchronous Hardware Clear Resets All Internal

Registers to Zero

MAX533

2.7V, Low-Power, 8-Bit Quad DAC

with Rail-to-Rail Output Buffers

________________________________________________________________

Maxim Integrated Products

OUTC

OUTD

AGND



DGND

DIN

SCLK

OUTB

OUTA

REF

UPO

PDE

LDAC

CLR

DOUT

TOP VIEW

MAX533

DIP/QSOP

__________________Pin Configuration

19-1080; Rev 0; 6/96

PART

MAX533ACPE

MAX533BCPE

MAX533ACEE 0°C to +70°C

0°C to +70°C

TEMP. RANGE PIN-PACKAGE

16 Plastic DIP

16 QSOP

______________Ordering Information

*Dice are tested at T

= +25°C.

**Contact factory for availability and processing to MIL-STD-883.

SPI and QSPI are trademarks of Motorola, Inc. Microwire is a trademark of National Semiconductor Corp.

Functional Diagram appears at end of data sheet.

For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800

MAX533BCEE 0°C to +70°C 16 QSOP

MAX533BC/D 0°C to +70°C Dice*

MAX533AEPE -40°C to +85°C 16 Plastic DIP

MAX533BEPE -40°C to +85°C 16 Plastic DIP

MAX533AEEE -40°C to +85°C 16 QSOP

MAX533BEEE -40°C to +85°C 16 QSOP

MAX533AMJE -55°C to +125°C 16 CERDIP**

MAX533BMJE -55°C to +125°C 16 CERDIP**

INL

(LSB)

±1

±2

±1

±2

±1

±2

±1

±2

±1

±2

Summary of content (16 pages)

PAGE 1
9-1080; Rev 0; 6/96 2.7V, Low-Power, 8-Bit Quad DAC with Rail-to-Rail Output Buffers ________________________Applications Digital Gain and Offset Adjustments Programmable Attenuators Programmable Current Sources ____________________________Features ♦ +2.7V to +3.6V Single-Supply Operation ♦ Ultra-Low Supply Current: 0.
PAGE 2
MAX533 2.7V, Low-Power, 8-Bit Quad DAC with Rail-to-Rail Output Buffers ABSOLUTE MAXIMUM RATINGS VDD to DGND ..............................................................-0.3V, +6V VDD to AGND...............................................................-0.3V, +6V Digital Input Voltage to DGND ....................................-0.3V, +6V Digital Output Voltage to DGND....................-0.3V, (VDD + 0.3V) AGND to DGND ..................................................................±0.3V REF ........
PAGE 3
2.7V, Low-Power, 8-Bit Quad DAC with Rail-to-Rail Output Buffers (VDD = +2.7V to +3.6V, VREF = 2.5V, AGND = DGND = 0V, RL = 10kΩ, CL = 100pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at VDD = +3V and TA = +25°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS DIGITAL INPUTS Input High Voltage VIH Input Low Voltage VIL 0.7VDD Input Current IIN VIN = 0V or VDD Input Capacitance CIN (Note 4) Output High Voltage VOH ISOURCE = TBDmA Output Low Voltage VOL ISINK = 1.
PAGE 4
MAX533 2.7V, Low-Power, 8-Bit Quad DAC with Rail-to-Rail Output Buffers TIMING CHARACTERISTICS (continued) (VDD = +2.7V to +3.6V, VREF = 2.5V, AGND = DGND = 0V, CDOUT = 100pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at VDD = +3V and TA = +25°C.
PAGE 5
2.7V, Low-Power, 8-Bit Quad DAC with Rail-to-Rail Output Buffers VDD = VREF = 3.0V 0.50 VDD = VREF = 5.0V 0.25 0 1 2 4 3 6 5 7 DAC CODE = FF HEX LOAD TO GND 3.5 3.0 400 DAC CODE = 00 HEX VDD = VREF = 3.0V 0 0 2 4 6 8 12 10 -55 -35 -15 5 25 45 65 85 105 125 DAC OUTPUT SOURCE CODE (mA) TEMPERATURE (°C) SHUTDOWN SUPPLY CURRENT vs. TEMPERATURE SUPPLY CURRENT vs. REFERENCE VOLTAGE (VDD = +3.0V) SUPPLY CURRENT vs. REFERENCE VOLTAGE (VDD = +5.0V) 800 VDD = +5.0V 2 VDD = +3.
PAGE 6
____________________________Typical Operating Characteristics (continued) (VDD = +3V, TA = +25°C, unless otherwise noted.) REFERENCE INPUT FREQUENCY RESPONSE REFERENCE FEEDTHROUGH vs. FREQUENCY -5 -10 -15 -20 VREF = 0.1Vp-p SINE WAVE CENTERED AT 2.5V DAC CODE = FF HEX VDD = +3.0V -25 -30 RELATIVE OUTPUT (dB) 0 MAX533-TOC12 -20 MAX533-TOC9 5 RELATIVE OUTPUT (dB) MAX533 2.7V, Low-Power, 8-Bit Quad DAC with Rail-to-Rail Output Buffers VDD = +3.
PAGE 7
2.7V, Low-Power, 8-Bit Quad DAC with Rail-to-Rail Output Buffers POSITIVE SETTLING TIME NEGATIVE SETTLING TIME MAX533-TOC15 MAX533-TOC16 CS 2V/div CS 2V/div OUTA 1V/div OUTA 1V/div 5µs/div VDD = 3.0V VREF = 2.5V 5µs/div VDD = 3.0V VREF = 2.
PAGE 8
MAX533 2.7V, Low-Power, 8-Bit Quad DAC with Rail-to-Rail Output Buffers INSTRUCTION EXECUTED CS ••• ••• SCLK ••• DIN A1 A0 C1 C0 A1 A0 C1 C0 D7 D6 D5 D4 D3 D2 D1 D0 MSB D7 D6 D5 D4 D3 D2 LSB MSB DACA LSB DACD ••• DOUT MODE 1 A1 A0 C1 C0 D7 D6 D5 D4 D3 D2 D1 D0 A1 A1 A0 C1 C0 DATA FROM PREVIOUS DATA INPUT DOUT MODE 0 (DEFAULT) D6 D5 D4 D3 D2 D1 D0 D7 A1 DATA FROM PREVIOUS DATA INPUT ••• A1 A0 C1 C0 D7 D6 D5 D4 D3 D2 D1 D0 A1 A1 A0 C1 C0 D6 D5 D4 D3 D2 D1 D0 D7 Figure 1.
PAGE 9
2.7V, Low-Power, 8-Bit Quad DAC with Rail-to-Rail Output Buffers Serial Interface At power-on, the serial interface and all digital-toanalog converters (DACs) are cleared and set to code zero. The serial data output (DOUT) is set to transition on SCLK's falling edge. The MAX533 communicates with microprocessors through a synchronous, full-duplex, 3-wire interface (Figure 1). Data is sent MSB first and can be transmitted in one 4-bit and one 8-bit (byte) packet or in one 12-bit word.
PAGE 10
MAX533 2.7V, Low-Power, 8-Bit Quad DAC with Rail-to-Rail Output Buffers 12-BIT SERIAL WORD A1 A0 C1 C0 D7 . . . . . . . . D0 LDAC 0 0 1 1 0 1 0 1 0 0 0 0 1 1 1 1 8-bit DAC data 8-bit DAC data 8-bit DAC data 8-bit DAC data 1 1 1 1 Load input register A; all DAC outputs unchanged. Load input register B; all DAC outputs unchanged. Load input register C; all DAC outputs unchanged. Load input register D; all DAC outputs unchanged.
PAGE 11
2.7V, Low-Power, 8-Bit Quad DAC with Rail-to-Rail Output Buffers Set DOUT Phase—SCLK Rising (Mode 1) A1 A0 C1 C0 D7 D6 D5 D4 D3 D2 D1 D0 1 1 1 0 x x x x x x x x Serial Data Output DOUT is the internal shift register’s output. DOUT can be programmed to clock out data on SCLK’s falling edge (mode 0) or rising edge (mode 1). In mode 0, output data lags input data by 12.5 clock cycles, maintaining compatibility with Microwire and SPI.
PAGE 12
MAX533 2.7V, Low-Power, 8-Bit Quad DAC with Rail-to-Rail Output Buffers Interfacing to the Microprocessor The MAX533 is Microwire™ and SPI™/QSPI™ compatible. For SPI and QSPI, clear the CPOL and CPHA configuration bits (CPOL = CPHA = 0). The SPI/QSPI CPOL = CPHA = 1 configuration can also be used if the DOUT output is ignored. The MAX533 can interface with Intel’s 80C5X/80C3X family in mode 0 if the SCLK clock polarity is inverted.
PAGE 13
2.7V, Low-Power, 8-Bit Quad DAC with Rail-to-Rail Output Buffers MAX533 DIN SCLK LDAC CS1 TO OTHER SERIAL DEVICES CS2 CS3 CS CS CS LDAC MAX533 LDAC MAX533 LDAC MAX533 SCLK SCLK SCLK DIN DIN DIN Figure 7. Multiple MAX533s sharing one DIN line. Simultaneously update by strobing LDAC, or specifically update by enabling an individual CS. Output Buffer Amplifiers All MAX533 voltage outputs are internally buffered by precision unity-gain followers that slew at about 0.6V/µs.
PAGE 14
REF R0 R1 R15 D7 R16 D6 D5 MSB DECODER MAX533 2.7V, Low-Power, 8-Bit Quad DAC with Rail-to-Rail Output Buffers OUTPUT VOLTAGE D4 R255 0V DAC CODE NEGATIVE OFFSET LSB DECODER D3 D2 D1 D0 DAC A Figure 8. DAC Simplified Circuit Diagram Power Sequencing The voltage applied to REF should not exceed VDD at any time. If proper power sequencing is not possible, connect an external Schottky diode between REF and VDD to ensure compliance with the absolute maximum ratings.
PAGE 15
2.7V, Low-Power, 8-Bit Quad DAC with Rail-to-Rail Output Buffers +3V 13 VDD MAX533 2 DAC A SYSTEM GND OUTC OUTB OUTD OUTA 1 OUTB DAC B SERIAL INTERFACE NOT SHOWN REF AGND OUTA 16 DAC C OUTC 15 DAC D OUTD DGND 12 AGND 14 Figure 10. Suggested PC Board Layout for Minimizing Crosstalk (Bottom View) Figure 11.
PAGE 16
2.7V, Low-Power, 8-Bit Quad DAC with Rail-to-Rail Output Buffers MAX533 ___________________Chip Information TRANSISTOR COUNT: 6821 ________________________________________________________Package Information DIM A A1 A2 B C D E e H h L N S α D A e A1 B S E INCHES MILLIMETERS MAX MIN MIN MAX 0.068 0.061 1.55 1.73 0.004 0.0098 0.127 0.25 0.061 0.055 1.40 1.55 0.012 0.008 0.20 0.31 0.0075 0.0098 0.19 0.25 SEE VARIATIONS 0.157 0.150 3.81 3.99 0.25 BSC 0.635 BSC 0.244 0.230 5.84 6.20 0.016 0.010 0.25 0.