Datasheet

MAX536/MAX537
Calibrated, Quad, 12-Bit
Voltage-Output DACs with Serial Interface
4 _______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS—MAX536 (continued)
(V
DD
= +12V, V
SS
= -5V, REFAB/REFCD = 8V, AGND = DGND = 0V, R
L
= 5kΩ, C
L
= 100pF, T
A
= T
MIN
to T
MAX
, unless
otherwise noted. Typical values are at T
A
= +25°C.)
PARAMETER
SYMBOL CONDITIONS MIN TYP MAX UNITS
t
POR
20
µs
SCK Clock Period t
CP
100 ns
SCK Pulse Width High t
CH
30 ns
SCK Pulse Width Low t
CL
30 ns
t
CSS
20 ns
t
CSH
10 ns
SDI Setup Time t
DS
40 26 ns
SDI Hold Time t
DH
0 ns
t
DO1
1kΩ pullup on SDO
to V
DD,
C
LOAD
=
50pF
SDO high 78 105
ns
SDO low
50 80
SCK Fall to SDO Valid
Propagation Delay (Note 7)
t
DO2
1kΩ pullup on SDO
to V
DD,
C
L
OAD
=
50pF
SDO high
81 110
ns
SDO low 53 85
t
DV
27 45 ns
t
TR
40 60 ns
SCK Rise to CS Fall Delay
t
CS0
Continuous SCK, SCK edge ignored 20 ns
t
CS1
SCK edge ignored 20 ns
LDAC Pulse Width Low
t
LDAC
30 ns
CS Pulse Width High
t
CSW
40 ns
Internal Power-On Reset
Pulse Width (Note 2)
CS Fall to SCK Rise
Setup Time
SCK Rise to CS Rise
Hold Time
SCK Rise to SDO Valid
Propagation Delay (Note 6)
CS Fall to SDO Enable
(Note 8)
CS Rise to SDO Disable
(Note 9)
CS Rise to SCK Rise
Hold Time
Note 1: TUE is specified with no resistive load.
Note 2: Guaranteed by design.
Note 3: Crosstalk is defined as the glitch energy at any DAC output in response to a full-scale step change on any other DAC
.
Note 4: Digital inputs at 2.4V; with digital inputs at CMOS levels, I
DD
decreases slightly.
Note 5: All input signals are specified with t
R
= t
F
≤ 5ns. Logic input swing is 0 to 5V.
Note 6: Serial data clocked out of SDO on SCK’s falling edge. (SDO is an open-drain output for the MAX536. The MAX537’s SDO
pin has an internal active pullup.)
Note 7: Serial data clocked out of SDO on SCK’s rising edge.
Note 8: SDO changes from High-Z state to 90% of final value.
Note 9: SDO rises 10% toward High-Z state.
TIMING CHARACTERISTICS (Note 5)