9-0230; Rev 3; 3/11 Calibrated, Quad, 12-Bit Voltage-Output DACs with Serial Interface The MAX536/MAX537 combine four 12-bit, voltage-output digital-to-analog converters (DACs) and four precision output amplifiers in a space-saving 16-pin package. Offset, gain, and linearity are factory calibrated to provide the MAX536’s ±1 LSB total unadjusted error. The MAX537 operates with ±5V supplies, while the MAX536 uses -5V and +10.8V to +13.2V supplies.
MAX536/MAX537 Calibrated, Quad, 12-Bit Voltage-Output DACs with Serial Interface ABSOLUTE MAXIMUM RATINGS VDD to AGND or DGND MAX536 ............................................................-0.3V to +13.2V MAX537 .................................................................-0.3V to +7V VSS to AGND or DGND ............................................-7V to +0.3V SDI, SCK , CS, LDAC, TP, SDO to AGND or DGND..................................-0.3V to (VDD + 0.3V) REFAB, REFCD to AGND or DGND ..........
Calibrated, Quad, 12-Bit Voltage-Output DACs with Serial Interface MAX536/MAX537 ELECTRICAL CHARACTERISTICS—MAX536 (continued) (VDD = +12V, VSS = -5V, REFAB/REFCD = 8V, AGND = DGND = 0V, RL = 5kΩ, CL = 100pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS MATCHING PERFORMANCE (TA = +25°C) Total Unadjusted Error TUE MAX536A ±1.0 MAX536B ±2.0 Gain Error Offset Error Integral Nonlinearity ±0.1 ±1.0 MAX536A ±1.2 ±2.
MAX536/MAX537 Calibrated, Quad, 12-Bit Voltage-Output DACs with Serial Interface ELECTRICAL CHARACTERISTICS—MAX536 (continued) (VDD = +12V, VSS = -5V, REFAB/REFCD = 8V, AGND = DGND = 0V, RL = 5kΩ, CL = 100pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.
Calibrated, Quad, 12-Bit Voltage-Output DACs with Serial Interface MAX536/MAX537 ELECTRICAL CHARACTERISTICS—MAX537 (VDD = +5V, VSS = -5V, REFAB/REFCD = 2.5V, AGND = DGND = 0V, RL = 5kΩ, CL = 100pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX ±0.15 ±0.
MAX536/MAX537 Calibrated, Quad, 12-Bit Voltage-Output DACs with Serial Interface ELECTRICAL CHARACTERISTICS—MAX537 (continued) (VDD = +5V, VSS = -5V, REFAB/REFCD = 2.5V, AGND = DGND = 0V, RL = 5kΩ, CL = 100pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER SYMBOL CONDITIONS MIN TYP VDD - VDD - 0.5 0.25 MAX UNITS DIGITAL OUTPUT (SDO) Output High Voltage VOH SDO sourcing 2mA Output Low Voltage VOL SDO sinking 2mA 0.13 V 0.
Calibrated, Quad, 12-Bit Voltage-Output DACs with Serial Interface (VDD = +5V, VSS = -5V, REFAB/REFCD = 2.5V, AGND = DGND = 0V, RL = 5kΩ, CL = 100pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.
__________________________________________Typical Operating Characteristics MAX536 (TA = +25°C, unless otherwise noted.) VDD = +15V -0.2 10 VDD = +12V 0.200 0.175 0.150 0 -10 -20 -30 -40 0 4 8 12 REFERENCE VOLTAGE (V) 100k 1M 10 10M RL = 10kΩ, CL = 100pF 0.075 RL = NO LOAD, CL = 0pF 10 0 6 SUPPLY CURRENT (mA) 0.
Calibrated, Quad, 12-Bit Voltage-Output DACs with Serial Interface MAX536 MAX536 DYNAMIC RESPONSE (ALL BITS ON, OFF, ON) MAX536 NEGATIVE FULL-SCALE SETTLING TIME (ALL BITS ON TO ALL BITS OFF) CS, 5V/div CS, 5V/div OUTA, 5V/div OUTA, 2V/div 5µs/div OUTA, 5mV/div 1µs/div VDD = +15V, VSS = -5V, REFAB = 5V, CL = 100pF, RL = 10kΩ VDD = +15V, VSS = -5V, REFAB = 10V, CL = 100pF, RL = 10kΩ MAX536 POSITIVE FULL-SCALE SETTLING TIME (ALL BITS OFF TO ALL BITS ON) MAX536 DIGITAL FEEDTHROUGH CS, 5V/div SCK,
____________________________Typical Operating Characteristics (continued) (TA = +25°C, unless otherwise noted.) MAX537 MAX537 REFERENCE VOLTAGE INPUT FREQUENCY RESPONSE 0.5 0 -0.5 -1.0 REFAB = 2.5VP-P 0.175 0.150 0 THD + NOISE (%) RELATIVE OUTPUT (dB) -10 -20 0.125 RL = 10kΩ, CL = 100pF 0.100 0.075 RL = NO LOAD, CL = 0pF -30 0.050 -1.5 -40 -2.0 -50 0 1 2 3 4 5 0.
Calibrated, Quad, 12-Bit Voltage-Output DACs with Serial Interface MAX537 MAX537 NEGATIVE FULL-SCALE SETTLING TIME (ALL BITS ON TO ALL BITS OFF) MAX537 DYNAMIC RESPONSE (ALL BITS ON, OFF, ON) CS, 5V/div CS, 5V/div OUTA, 5mV/div OUTA, 1V/div 5µs/div 1µs/div VDD = +5V, VSS = -5V, REFAB = 2.5V, CL = 100pF, RL = 10kΩ VDD = +5V, VSS = -5V, REFAB = 2.
MAX536/MAX537 Calibrated, Quad, 12-Bit Voltage-Output DACs with Serial Interface ______________________________________________________________Pin Description PIN NAME FUNCTION 1 OUTB DAC B Output Voltage 2 OUTA DAC A Output Voltage 3 VSS Negative Power Supply 4 AGND Analog Ground 5 REFAB Reference Voltage Input for DAC A and DAC B 6 DGND Digital Ground 7 LDAC Load DAC Input (active low).
Calibrated, Quad, 12-Bit Voltage-Output DACs with Serial Interface is 5µs when loaded with 5kΩ in parallel with 100pF (loads less than 5kΩ degrade performance). Output dynamic responses and settling performances of the MAX536/MAX537 output amplifier are shown in the Typical Operating Characteristics. The REFAB and REFCD reference inputs have a 5kΩ guaranteed minimum input impedance. When the two reference inputs are driven from the same source, the effective minimum impedance becomes 2.5kΩ.
MAX536/MAX537 Calibrated, Quad, 12-Bit Voltage-Output DACs with Serial Interface ;;; ;; ; ;;;; CS COMMAND EXECUTED SCK 1 8 9 16 SDI ..........D2 D1 D0 D15 D14 D13.......... MSB LSB SDO ...........Q0 Q15.......... MSB FROM PREVIOUS WRITE LSB FROM PREVIOUS WRITE Figure 4. 3-Wire Serial-Interface Timing Diagram (LDAC = GND or VDD) CS INPUT REGISTER(S) UPDATED SCK 1 8 9 16 SDI .......... D2 D1 D0 D15 D14 D13 .......... MSB LSB SDO Q15.......... ..........
Calibrated, Quad, 12-Bit Voltage-Output DACs with Serial Interface Serial-Interface Description The MAX536/MAX537 require 16 bits of serial data. Data is sent MSB first and can be sent in two 8-bit packets or one 16-bit word (CS must remain low until 16 bits are transferred). The serial data is composed of two DAC address bits (A1, A0), two control bits (C1, C0), and the 12 data bits D11…D0 (Figure 7).
MAX536/MAX537 Calibrated, Quad, 12-Bit Voltage-Output DACs with Serial Interface Table 1. Serial-Interface Programming Commands 16-BIT SERIAL WORD D11…D0 LDAC FUNCTION A1 A0 C1 C0 0 0 0 1 12-bit DAC data 1 Load DAC A input register; DAC output unchanged. 0 1 0 1 12-bit DAC data 1 Load DAC B input register; DAC output unchanged. 1 0 0 1 12-bit DAC data 1 Load DAC C input register; DAC output unchanged.
Calibrated, Quad, 12-Bit Voltage-Output DACs with Serial Interface +5V RP* 1kΩ +5V RP* 1kΩ RP* 1kΩ MAX536 MAX536 MAX536 SCK SCK MAX537 SCK MAX537 SCK MAX537 DIN SDI CS CS SDO SDO SDI MAX536/MAX537 +5V CS SDI SDO CS TO OTHER SERIAL DEVICES * THE MAX537 HAS AN ACTIVE INTERNAL PULLUP, SO RP IS NOT NECESSARY. Figure 8.
MAX536/MAX537 Calibrated, Quad, 12-Bit Voltage-Output DACs with Serial Interface __________Applications Information Interfacing to the M68HC11* PORT D of the 68HC11 supports SPI. The four registers used for SPI operation are the Serial Peripheral Control Register, the Serial Peripheral Status Register, the Serial Peripheral Data I/O Register, and PORT D’s Data Direction Register. These registers have a default starting location of $1000.
Calibrated, Quad, 12-Bit Voltage-Output DACs with Serial Interface MAX536/MAX537 Table 4.
MAX536/MAX537 Calibrated, Quad, 12-Bit Voltage-Output DACs with Serial Interface SS is an input intended for use in a multimaster environment. However, SS or unused PORT D bit RXD, TXD, or possibly MISO (if DAC readback is not used) should be configured as a general-purpose output and used as CS by setting the appropriate Data Direction Register bit.
Calibrated, Quad, 12-Bit Voltage-Output DACs with Serial Interface 5 +12V (+5V) REFERENCE INPUTS 12 REFAB MAX536/MAX537 MAX536 MAX537 13 14 MAX536 MAX537 TP VDD REFCD R1 2 DAC A R2 VREF OUTA +12V (+5V) 1 DAC B OUTB VOUT 16 DAC C OUTC DAC OUTPUT –5V 15 DAC D VSS AGND 4 3 -5V R1 = R2 = 10kΩ 0.1% OUTD DGND 6 NOTES: ( ) ARE FOR MAX537. VREF IS THE SELECTED REFERENCE INPUT FOR THE MAX536/MAX537. NOTE: ( ) ARE FOR MAX537. Figure 10. Unipolar Output Circuit Figure 11.
Calibrated, Quad, 12-Bit Voltage-Output DACs with Serial Interface MAX536/MAX537 Offsetting AGND AGND can be biased from DGND to the reference voltage to provide an arbitrary nonzero output voltage for a zero input code (Figure 13). The output voltage VOUTA is: 3 VOUTA = VBIAS + NB (VIN) VSS MAX536 MAX537 1N5817 4 AGND where VBIAS is the positive offset voltage (with respect to DGND) applied to AGND, and NB is the numeric value of the DAC’s binary input code.
Calibrated, Quad, 12-Bit Voltage-Output DACs with Serial Interface PART TEMP RANGE PINPACKAGE INL (LSB) ±0.5 Package Information For the latest package outline information and land patterns (footprints), go to www.maxim-ic.com/packages. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status.
MAX536/MAX537 Calibrated, Quad, 12-Bit Voltage-Output DACs with Serial Interface Revision History REVISION NUMBER REVISION DATE 0 1/94 Initial release 3/11 Removed dice and ceramic SB packages and changed voltage supply specifications 3 DESCRIPTION PAGES CHANGED — 1–7, 13, 21, 22, 23 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied.