Datasheet

ManualsBrandsMAXIM INTEGRATED ManualsData collecting ICsData acquisition IC - DA converter (DAC) TSSOP 20

General Description

The MAX5580–MAX5585 quad, 12-/10-/8-bit, voltage-

output, digital-to-analog converters (DACs) offer

buffered outputs and a 3µs maximum settling time at the

12-bit level. The DACs operate from a +2.7V to +5.25V

analog supply and a separate +1.8V to +5.25V digital

supply. The 20MHz, 3-wire, serial interface is compati-

ble with SPI™, QSPI™, MICROWIRE™, and digital sig-

nal processor (DSP) protocol applications. Multiple

devices can share a common serial interface in direct-

access or daisy-chained configuration. The MAX5580–

MAX5585 provide two multifunctional, user-programma-

ble, digital I/O ports. The externally selectable power-up

states of the DAC outputs are either zero scale, mid-

scale, or full scale. Software-selectable FAST and SLOW

settling modes decrease settling time in FAST mode, or

reduce supply current in SLOW mode.

The MAX5580/MAX5581 are 12-bit DACs, the

MAX5582/MAX5583 are 10-bit DACs, and the

MAX5584/MAX5585 are 8-bit DACs. The MAX5580/

MAX5582/MAX5584 provide unity-gain-configured out-

put buffers, while the MAX5581/MAX5583/MAX5585

provide force-sense-configured output buffers. The

MAX5580–MAX5585 operate over the extended -40°C

to +85°C temperature range and are available in a

space-saving, 6.5mm x 4.4mm, 20-pin, TSSOP package.

Features

♦ 3µs (max) 12-Bit Settling Time to 0.5 LSB

♦ Quad, 12-/10-/8-Bit Serial DACs in TSSOP

Package

♦ ±1 LSB (max) INL and DNL at 12-Bit Resolution

♦ Two User-Programmable Digital I/O Ports

♦ Single +2.7V to +5.25V Analog Supply

♦ +1.8V to AV

Digital Supply

♦ 20MHz, 3-Wire, SPI-/QSPI-/MICROWIRE-/DSP-

Compatible Serial Interface

♦ Glitch-Free Outputs Power Up to Zero Scale,

Midscale, or Full Scale Controlled by PU Pin

♦ Unity-Gain or Force-Sense-Configured

Output Buffers

Applications

Portable Instrumentation

Automatic Test Equipment (ATE)

Digital Offset and Gain Adjustment

Automatic Tuning

Programmable Voltage and Current Sources

Programmable Attenuators

Industrial Process Controls

Motion Control

Microprocessor (µP)-Controlled Systems

Power Amplifier Control

Fast Parallel-DAC to Serial-DAC Upgrades

MAX5580–MAX5585

Buffered, Fast-Settling, Quad,

12-/10-/8-Bit, Voltage-Output DACs

________________________________________________________________

Maxim Integrated Products

19-3164; Rev 4; 7/08

For pricing delivery, and ordering information please contact Maxim Direct at 1-888-629-4642,

or visit Maxim’s website at www.maxim-ic.com.

Pin Configuration appears at end of data sheet.

EVALUATION KIT

AVAILABLE

SPI/QSPI are trademarks of Motorola, Inc.

MICROWIRE is a trademark of National Semiconductor Corp.

PART

RESOLUTION

(BITS)

INL

(LSB max)

OUTPUT BUFFER

CONFIGURATION

PIN-PACKAGE

MAX5580AEUP+ 12 ±1 Unity gain 20 TSSOP-EP*

MAX5580BEUP+ 12 ±4 Unity gain 20 TSSOP-EP*

MAX5581AEUP+ 12 ±1 Force sense 20 TSSOP-EP*

MAX5581BEUP+ 12 ±4 Force sense 20 TSSOP-EP*

MAX5582EUP+ 10 ±1 Unity gain 20 TSSOP-EP*

MAX5583EUP+ 10 ±1 Force sense 20 TSSOP-EP*

MAX5584EUP+ 8 ±0.5 Unity gain 20 TSSOP-EP*

MAX5585EUP+ 8 ±0.5 Force sense 20 TSSOP-EP*

Ordering Information/Selector Guide

Denotes a lead-free/RoHS-compliant package.

EP = Exposed paddle.

Note: All devices are specified over the -40°C to +85°C operating temperature range.

Summary of content (34 pages)

PAGE 1
9-3164; Rev 4; 7/08 KIT ATION EVALU LE B A IL A AV Buffered, Fast-Settling, Quad, 12-/10-/8-Bit, Voltage-Output DACs Features ♦ 3µs (max) 12-Bit Settling Time to 0.5 LSB ♦ Quad, 12-/10-/8-Bit Serial DACs in TSSOP Package ♦ ±1 LSB (max) INL and DNL at 12-Bit Resolution ♦ Two User-Programmable Digital I/O Ports ♦ Single +2.7V to +5.25V Analog Supply ♦ +1.
PAGE 2
MAX5580–MAX5585 Buffered, Fast-Settling, Quad, 12-/10-/8-Bit, Voltage-Output DACs ABSOLUTE MAXIMUM RATINGS AVDD to DVDD ........................................................................±6V AGND to DGND ..................................................................±0.3V AVDD to AGND, DGND.............................................-0.3V to +6V DVDD to AGND, DGND ............................................-0.3V to +6V FB_, OUT_, REF to AGND ........-0.3V to the lower of (AVDD + 0.
PAGE 3
Buffered, Fast-Settling, Quad, 12-/10-/8-Bit, Voltage-Output DACs (AVDD = 2.7V to 5.25V, DVDD = 1.8V to AVDD, VAGND = 0, VDGND = 0, VREF = 2.5V (for AVDD = 2.7V to 5.25V), VREF = 4.096V (for AVDD = 4.5V to 5.25V), RL = 10kΩ, CL = 100pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1) PARAMETER SYMBOL Power-Supply Rejection Ratio PSRR CONDITIONS MIN Full-scale output, AVDD = 2.7V to 5.
PAGE 4
MAX5580–MAX5585 Buffered, Fast-Settling, Quad, 12-/10-/8-Bit, Voltage-Output DACs ELECTRICAL CHARACTERISTICS (continued) (AVDD = 2.7V to 5.25V, DVDD = 1.8V to AVDD, VAGND = 0, VDGND = 0, VREF = 2.5V (for AVDD = 2.7V to 5.25V), VREF = 4.096V (for AVDD = 4.5V to 5.25V), RL = 10kΩ, CL = 100pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.
PAGE 5
Buffered, Fast-Settling, Quad, 12-/10-/8-Bit, Voltage-Output DACs (AVDD = 2.7V to 5.25V, DVDD = 1.8V to AVDD, VAGND = 0, VDGND = 0, VREF = 2.5V (for AVDD = 2.7V to 5.25V), VREF = 4.096V (for AVDD = 4.5V to 5.25V), RL = 10kΩ, CL = 100pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS POWER REQUIREMENTS Analog Supply Voltage Range AVDD 2.70 5.25 V Digital Supply Voltage Range DVDD 1.
PAGE 6
MAX5580–MAX5585 Buffered, Fast-Settling, Quad, 12-/10-/8-Bit, Voltage-Output DACs TIMING CHARACTERISTICS—DSP Mode Disabled (3V, 3.3V, 5V Logic) (Figure 1) (DVDD = 2.7V to 5.25V, AGND = DGND = 0, TA = TMIN to TMAX, unless otherwise noted.) PARAMETER SYMBOL SCLK Frequency SCLK Pulse-Width High fSCLK CONDITIONS MIN TYP 2.7V < DVDD < 5.
PAGE 7
Buffered, Fast-Settling, Quad, 12-/10-/8-Bit, Voltage-Output DACs (DVDD = 1.8V to 2.7V, AGND = DGND = 0, TA = TMIN to TMAX, unless otherwise noted.) PARAMETER SYMBOL SCLK Frequency fSCLK CONDITIONS MIN 1.8V < DVDD < 2.
PAGE 8
MAX5580–MAX5585 Buffered, Fast-Settling, Quad, 12-/10-/8-Bit, Voltage-Output DACs TIMING CHARACTERISTICS—DSP Mode Enabled (3V, 3.3V, 5V Logic) (Figure 2) (DVDD = 2.7V to 5.25V, AGND = DGND = 0, TA = TMIN to TMAX, unless otherwise noted.) PARAMETER SYMBOL SCLK Frequency SCLK Pulse-Width High fSCLK CONDITIONS MIN TYP 2.7V < DVDD < 5.
PAGE 9
Buffered, Fast-Settling, Quad, 12-/10-/8-Bit, Voltage-Output DACs (DVDD = 1.8V to 2.7V, AGND = DGND = 0, TA = TMIN to TMAX, unless otherwise noted.) PARAMETER SYMBOL SCLK Frequency fSCLK CONDITIONS MIN 1.8V < DVDD < 2.
PAGE 10
Typical Operating Characteristics (AVDD = DVDD = 5V, VREF = 4.096V, RL = 10kΩ, CL = 100pF, speed mode = FAST, PU = floating, TA = +25°C, unless otherwise noted.) 0.5 0.4 0.3 3 2 0.2 0.2 0.1 1 INL (LSB) INL (LSB) 0.3 INL (LSB) 4 MAX5580-85 toc02 0.4 MAX5580-85 toc01 0.6 INTEGRAL NONLINEARITY vs. DIGITAL INPUT CODE (12 BIT) INTEGRAL NONLINEARITY vs. DIGITAL INPUT CODE (MAX5581A) 0.1 0 MAX5580-85 toc03 INTEGRAL NONLINEARITY vs. DIGITAL INPUT CODE (MAX5580A) 0 -1 0 -2 -0.1 -0.1 -3 -0.
PAGE 11
Buffered, Fast-Settling, Quad, 12-/10-/8-Bit, Voltage-Output DACs INTEGRAL NONLINEARITY vs. REFERENCE VOLTAGE (MAX5581A) 0.8 3 2 0.7 0.4 0.3 DNL (LSB) INL (LSB) 0 -1 -2 0.1 -3 0 -4 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 -0.3 B GRADE MIDSCALE 1.0 1.5 -0.4 2.0 2.5 VREF (V) INTEGRAL NONLINEARITY vs. TEMPERATURE (12 BIT) 3.0 3.5 VREF (V) 4.0 4.5 0 -1 -2 0 -0.1 B GRADE MIDSCALE 3.0 3.5 4.0 4.5 1.5 5.0 1.0 0.5 SLOW MODE 12 BIT NO LOAD MIDSCALE -4 2.5 2.
PAGE 12
Typical Operating Characteristics (continued) (AVDD = DVDD = 5V, VREF = 4.096V, RL = 10kΩ, CL = 100pF, speed mode = FAST, PU = floating, TA = +25°C, unless otherwise noted.) 90 85 0.4 INL (LSB) UNITY GAIN 75 FORCE SENSE 70 55 1.5 1.0 0.5 0.1 50 0 0 2.70 3.40 4.10 4.80 5.25 -40 -15 10 35 60 TEMPERATURE (°C) OFFSET ERROR vs. TEMPERATURE GAIN ERROR vs. TEMPERATURE (A GRADE) FORCE SENSE 3 MAX5580-85 toc23 -0.5 -1.0 -1.
PAGE 13
Buffered, Fast-Settling, Quad, 12-/10-/8-Bit, Voltage-Output DACs REFERENCE INPUT BANDWIDTH MAX5580-85 toc28 REFERENCE FEEDTHROUGH AT 1kHz FULL-SCALE TRANSITION 0 -5 GAIN (dB) CS 2V/div -22 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 MAX5580-85 toc29 5 -10 -15 OUT_ 2V/div -20 VREF = 0.1VP-P AT 4.096VDC UNITY GAIN -25 -142 1 400ns/div 10 100 1k 10k 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.
PAGE 14
MAX5580–MAX5585 Buffered, Fast-Settling, Quad, 12-/10-/8-Bit, Voltage-Output DACs Pin Description PIN MAX5580 MAX5582 MAX5584 MAX5581 MAX5583 MAX5585 NAME 1 1 AGND Analog Ground 2 2 AVDD Analog Supply 3, 5, 17, 19 — N.C. No Connection. Not internally connected. 14 FUNCTION — 3 FBB 4 4 OUTB Feedback for DACB — 5 FBA 6 6 OUTA 7 7 PU Power-Up State Select Input. Connect PU to DVDD to set OUT_ to full scale upon power-up.
PAGE 15
Buffered, Fast-Settling, Quad, 12-/10-/8-Bit, Voltage-Output DACs AVDD CS SCLK DIN DSP DVDD AGND DGND SERIAL INTERFACE CONTROL MAX5580 MAX5582 MAX5584 16-BIT SHIFT REGISTER MUX UPIO1 UPIO2 PU UPIO1 AND UPIO2 LOGIC DOUT REGISTER POWER-DOWN LOGIC AND REGISTER DECODE CONTROL OUTA INPUT REGISTER A DAC REGISTER A INPUT REGISTER D DAC REGISTER D DACA OUTD DACD REF ______________________________________________________________________________________ 15 MAX5580–MAX5585 Functional Diagrams
PAGE 16
Buffered, Fast-Settling, Quad, 12-/10-/8-Bit, Voltage-Output DACs MAX5580–MAX5585 Functional Diagrams (continued) AVDD CS SCLK DIN DSP DVDD AGND DGND SERIAL INTERFACE CONTROL MAX5581 MAX5583 MAX5585 16-BIT SHIFT REGISTER MUX UPIO1 UPIO2 PU UPIO1 AND UPIO2 LOGIC DOUT REGISTER POWER-DOWN LOGIC AND REGISTER FBA DECODE CONTROL OUTA INPUT REGISTER A DAC REGISTER A DACA FBD OUTD INPUT REGISTER D DAC REGISTER D DACD REF 16 _________________________________________________________________
PAGE 17
Buffered, Fast-Settling, Quad, 12-/10-/8-Bit, Voltage-Output DACs The MAX5580–MAX5585 quad, 12-/10-/8-bit, voltageoutput DACs offer buffered outputs and a 3µs maximum settling time at the 12-bit level. The DACs operate from a single 2.7V to 5.25V analog supply and a separate 1.8V to AVDD digital supply. The MAX5580–MAX5585 include an input register and DAC register for each channel and a 16-bit data-in/data-out shift register.
PAGE 18
MAX5580–MAX5585 Buffered, Fast-Settling, Quad, 12-/10-/8-Bit, Voltage-Output DACs Table 1. Serial Write Data Format MSB 16 BITS OF SERIAL DATA CONTROL BITS C3 C2 C1 LSB DATA BITS C0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 tCH SCLK tCL tDS DIN C3 tCS0 C2 C1 D0 tCSH tDH tCSS CS tCSW tCS1 tDO1 DOUTDC1* DOUT VALID tDO2 DOUTDC0 OR DOUTRB* DOUT VALID *UPIO1/UPIO2 CONFIGURED AS DOUTDC_ (DAISY-CHAIN DATA OUTPUT, MODE 0 OR 1) OR DOUTRB (READ-BACK DATA OUTPUT).
PAGE 19
Buffered, Fast-Settling, Quad, 12-/10-/8-Bit, Voltage-Output DACs Loading Input and DAC Registers The MAX5580–MAX5585 contain a 16-bit shift register that is followed by a 12-bit input register and a 12-bit DAC register for each channel (see the Functional Diagrams). Tables 3, 4, and 5 highlight a few of the commands that handle the loading of the input and DAC registers. See Table 2a for all DAC programming commands.
PAGE 20
C3 C2 C1 0 0 0 0 0 0 0 0 1 1 1 DIN DIN DIN DIN DIN DIN DIN DIN DIN DIN DIN ______________________________________________________________________________________ 0 0 0 1 1 1 1 0 0 0 0 1 0 0 1 1 0 0 1 1 0 0 0 1 0 1 0 1 0 1 0 1 0 C0 CONTROL BITS INPUT REGISTERS (A–D) DATA D11 D10 D11 D10 D11 D10 D11 D10 D11 D10 D11 D10 D11 D10 D11 D10 D11 D10 D11 D10 D11 D10 D11 D10 D9 D9 D9 D9 D9 D9 D9 D9 D9 D9 D9 D9 D8 D8 D8 D8 D8
PAGE 21
C3 C2 C1 1 DIN 1 0 0 1 0 D11 D10 D11 D10 D11 D10 D9 D9 D9 D8 D8 D8 D7 D7 D7 D6 D6 D6 D5 D5 D5 DATA BITS D4 D4 D4 D2 D1 D0 Load DACD input register and output register from shift register; DACD output is updated.* FUNCTION Load all DAC input registers from the shift D3/0 D2/0 D1/0 D0/0 register; all DAC output registers are unchanged; all DAC outputs are unchanged.
PAGE 22
1 X X C2 1 C3 1 X DIN DOUTR X 1 1 X 1 1 X 1 1 X 0 C0 X 0 0 X 1 D11 X DOUTRB X 1 1 1 1 DIN DIN DIN X = Don’t care.
PAGE 23
1 X 1 X 1 X DIN DOUTRB DIN DOUTRB DIN DOUTRB X 1 X 1 X 1 X 1 X 1 X 1 X 1 X 1 X 1 X 1 X 1 X 1 X 1 X 1 X 0 X 0 X 0 X 0 X 1 X 1 X 1 X 0 X 1 X 0 X X X X X X X X 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 X X X X X X X X X X X X X X X X X X X X X X X X X X X X 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 (all 24 bit
PAGE 24
MAX5580–MAX5585 Buffered, Fast-Settling, Quad, 12-/10-/8-Bit, Voltage-Output DACs Advanced-Feature Programming Commands DAC Programming Examples: To load input register A from the shift register, leaving DAC register A unchanged (DAC output unchanged), use the command in Table 3. The MAX5580–MAX5585 can load all the input registers (A–D) simultaneously from the shift register, leaving the DAC registers unchanged (DAC output unchanged), by using the command in Table 4.
PAGE 25
Buffered, Fast-Settling, Quad, 12-/10-/8-Bit, Voltage-Output DACs 1kΩ output impedance, and 3) shutdown with 100kΩ output impedance. The three possible states for forcesense versions are 1) normal operation, 2) shutdown with 1kΩ output impedance, and 3) shutdown with the output in a high-impedance state. Table 9 shows the commands for writing to the shutdown-mode bits. Table 10 shows an example of writing the shutdown-control bits.
PAGE 26
MAX5580–MAX5585 Buffered, Fast-Settling, Quad, 12-/10-/8-Bit, Voltage-Output DACs ing edge of SCLK. Set the DAC’s CPOL and CPHA bits to CPOL = 0 and CPHA = 1 or CPOL = 1 and CPHA = 0 for DSP and SPI applications, requiring the clocking of data in on the falling edge of SCLK (refer to the Programmer’s Handbook and see Table 14 for details). At power-up, if DSP = DVDD, the default value of CPHA is zero and if DSP = DGND, the default value of CPHA is one. The default value of CPOL is zero at power-up.
PAGE 27
Buffered, Fast-Settling, Quad, 12-/10-/8-Bit, Voltage-Output DACs UPIO Programming Example: To set only UPIO1 as LDAC and leave UPIO2 unchanged, use the command in Table 19. The UPIO selection and configuration bits can be read back from the MAX5580–MAX5585 when UPIO1 or UPIO2 is configured as a DOUTRB output. Table 20 shows the read-back data format for the UPIO bits. Writing the command in Table 20 initiates a read operation of the UPIO bits.
PAGE 28
MAX5580–MAX5585 Buffered, Fast-Settling, Quad, 12-/10-/8-Bit, Voltage-Output DACs UPIO Configuration Table 21 lists the possible configurations for UPIO1 and UPIO2. UPIO1 and UPIO2 use the selected function when configured by the UP3–UP0 configuration bits. LDAC LDAC controls the loading of the DAC registers. When LDAC is high, the DAC registers are latched, and any change in the input registers does not affect the contents of the DAC registers or the DAC outputs.
PAGE 29
Buffered, Fast-Settling, Quad, 12-/10-/8-Bit, Voltage-Output DACs MAX5580–MAX5585 tLDL LDAC END OF CYCLE* TOGG tGP GPO_ PDL LDAC tCMS tLDS CLR, MID, OR SET tS ±0.5 LSB * END-OF-CYCLE REPRESENTS THE RISING EDGE OF CS OR THE 16TH ACTIVE CLOCK EDGE, DEPENDING ON THE MODE OF OPERATION. VOUT_ PDL AFFECTS DAC OUTPUTS (VOUT_) ONLY IF DACS WERE PREVIOUSLY SHUT DOWN. Figure 5. Asynchronous Signal Timing Figure 6.
PAGE 30
MAX5580–MAX5585 Buffered, Fast-Settling, Quad, 12-/10-/8-Bit, Voltage-Output DACs GPI, GPOL, GPOH UPIO1 and UPIO2 can each be configured as a general-purpose input (GPI), a general-purpose output low (GPOL), or a general-purpose output high (GPOH). The GPI can serve to detect interrupts from µPs or microcontrollers. The GPI has three functions: GPOL outputs a constant low, and GPOH outputs a constant high. See Figure 6.
PAGE 31
Buffered, Fast-Settling, Quad, 12-/10-/8-Bit, Voltage-Output DACs Unipolar Output Figure 7 shows the unity-gain MAX5580 in a unipolar output configuration. Table 23 lists the unipolar output codes. 10kΩ 10kΩ V+ Bipolar Output The MAX5580 outputs can be configured for bipolar operation, as shown in Figure 8. The output voltage is given by the following equation: VOUT_ = VREF x (CODE - 2048) / 2048 where CODE represents the numeric value of the DAC’s binary input code (0 to 4095 decimal).
PAGE 32
MAX5580–MAX5585 Buffered, Fast-Settling, Quad, 12-/10-/8-Bit, Voltage-Output DACs Power-Supply and Layout Considerations Bypass the analog and digital power supplies by using a 10µF capacitor in parallel with a 0.1µF capacitor to AGND and DGND (Figure 10). Minimize lead lengths to reduce lead inductance. Use shielding and/or ferrite beads to further increase isolation. Digital and AC transient signals coupling to AGND can create noise at the output. Connect AGND to the highest quality ground available.
PAGE 33
Buffered, Fast-Settling, Quad, 12-/10-/8-Bit, Voltage-Output DACs Chip Information TRANSISTOR COUNT: 24,393 PROCESS: BiCMOS TOP VIEW AGND 1 20 REF AVDD 2 19 N.C. (*FBC) Package Information 18 OUTC N.C. (*FBB) 3 17 N.C. (*FBD) OUTB 4 MAX5580– MAX5585 N.C. (*FBA) 5 OUTA 6 16 OUTD 15 DSP PU 7 14 DGND CS 8 13 DVDD SCLK 9 For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. PACKAGE TYPE PACKAGE CODE DOCUMENT NO.
PAGE 34
MAX5580–MAX5585 Buffered, Fast-Settling, Quad, 12-/10-/8-Bit, Voltage-Output DACs Revision History REVISION NUMBER REVISION DATE 3 7/07 Updated EC table specs 4 7/08 Removed TQFN information from data sheet DESCRIPTION PAGES CHANGED 6–9 1, 2, 14, 33–36 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied.