9-2983; Rev 3; 1/10 KIT ATION EVALU E L B AVAILA Buffered, Fast-Settling, Octal, 12/10/8-Bit, Voltage-Output DACs Features The MAX5590–MAX5595 octal, 12/10/8-bit, voltage-output digital-to-analog converters (DACs) offer buffered outputs and a 3µs maximum settling time at the 12-bit level. The DACs operate from a +2.7V to +5.25V analog supply and a separate +1.8V to +5.25V digital supply.
MAX5590–MAX5595 Buffered, Fast-Settling, Octal, 12/10/8-Bit, Voltage-Output DACs ABSOLUTE MAXIMUM RATINGS AVDD to DVDD ........................................................................±6V AGND to DGND ..................................................................±0.3V AVDD to AGND, DGND.............................................-0.3V to +6V DVDD to AGND, DGND ............................................-0.3V to +6V FB_, OUT_, REF to AGND ........-0.3V to the lower of (AVDD + 0.
Buffered, Fast-Settling, Octal, 12/10/8-Bit, Voltage-Output DACs (AVDD = 2.7V to 5.25V, DVDD = 1.8V to AVDD, VAGND = 0V, VDGND = 0V, VREF = 2.5V (for AVDD = 2.7V to 5.25V), VREF = 4.096V (for AVDD = 4.5V to 5.25V), RL = 10kΩ, CL = 100pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1) PARAMETER SYMBOL Power-Supply Rejection Ratio PSRR CONDITIONS MIN Full-scale output, AVDD = 2.7V to 5.
MAX5590–MAX5595 Buffered, Fast-Settling, Octal, 12/10/8-Bit, Voltage-Output DACs ELECTRICAL CHARACTERISTICS (continued) (AVDD = 2.7V to 5.25V, DVDD = 1.8V to AVDD, VAGND = 0V, VDGND = 0V, VREF = 2.5V (for AVDD = 2.7V to 5.25V), VREF = 4.096V (for AVDD = 4.5V to 5.25V), RL = 10kΩ, CL = 100pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.
Buffered, Fast-Settling, Octal, 12/10/8-Bit, Voltage-Output DACs (AVDD = 2.7V to 5.25V, DVDD = 1.8V to AVDD, VAGND = 0V, VDGND = 0V, VREF = 2.5V (for AVDD = 2.7V to 5.25V), VREF = 4.096V (for AVDD = 4.5V to 5.25V), RL = 10kΩ, CL = 100pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS POWER REQUIREMENTS Analog Supply Voltage Range AVDD 2.70 5.25 V Digital Supply Voltage Range DVDD 1.
MAX5590–MAX5595 Buffered, Fast-Settling, Octal, 12/10/8-Bit, Voltage-Output DACs TIMING CHARACTERISTICS—DSP Mode Disabled (3V, 3.3V, 5V Logic) (Figure 1) (DVDD = 2.7V to 5.25V, VAGND = 0V, VDGND = 0V, TA = TMIN to TMAX, unless otherwise noted.) PARAMETER SYMBOL SCLK Frequency SCLK Pulse-Width High fSCLK CONDITIONS MIN TYP 2.7V < DVDD < 5.
Buffered, Fast-Settling, Octal, 12/10/8-Bit, Voltage-Output DACs (DVDD = 1.8V to 5.25V, VAGND = 0V, VDGND = 0V, TA = TMIN to TMAX, unless otherwise noted.) PARAMETER SYMBOL SCLK Frequency fSCLK CONDITIONS MIN 1.8V < DVDD < 5.
MAX5590–MAX5595 Buffered, Fast-Settling, Octal, 12/10/8-Bit, Voltage-Output DACs TIMING CHARACTERISTICS—DSP Mode Enabled (3V, 3.3V, 5V Logic) (Figure 2) (DVDD = 2.7V to 5.25V, VAGND = 0V, VDGND = 0V, TA = TMIN to TMAX, unless otherwise noted.) PARAMETER SYMBOL SCLK Frequency SCLK Pulse-Width High fSCLK CONDITIONS MIN TYP 2.7V < DVDD < 5.
Buffered, Fast-Settling, Octal, 12/10/8-Bit, Voltage-Output DACs (DVDD = 1.8V to 5.25V, VAGND = 0V, VDGND = 0V, TA = TMIN to TMAX, unless otherwise noted.) PARAMETER SYMBOL SCLK Frequency fSCLK SCLK Pulse-Width High CONDITIONS MIN 1.8V < DVDD < 5.
Typical Operating Characteristics (AVDD = DVDD = 5V, VREF = 4.096V, RL = 10kΩ, CL = 100pF, speed mode = FAST, PU = unconnected, TA = +25°C, unless otherwise noted.) 3 2 0.50 MAX5590-95 toc02 1.00 MAX5590-95 toc01 4 0.75 0.50 0.25 0 0 -1 -0.25 -2 -0.50 -3 INL (LSB) 0.25 1 INL (LSB) INL (LSB) INTEGRAL NONLINEARITY vs. DIGITAL INPUT CODE (8-BIT) INTEGRAL NONLINEARITY vs. DIGITAL INPUT CODE (10-BIT) MAX5590-95 toc03 INTEGRAL NONLINEARITY vs. DIGITAL INPUT CODE (12-BIT) 0 -0.25 -0.
Buffered, Fast-Settling, Octal, 12/10/8-Bit, Voltage-Output DACs -0.1 MAX5590-95 toc12 1 12-BIT NO LOAD 12-BIT NO LOAD 0 -15 10 35 60 85 0 1024 2048 3072 0 4095 0 1024 2048 3072 4095 TEMPERATURE (°C) DIGITAL INPUT CODE DIGITAL INPUT CODE SUPPLY CURRENT vs. SUPPLY VOLTAGE (FORCE-SENSE) SUPPLY CURRENT vs. SUPPLY VOLTAGE (UNITY GAIN) SHUTDOWN SUPPLY CURRENT vs. SUPPLY VOLTAGE 2 1 2.0 1.0 0.5 AVDD = DVDD NO LOAD 0 SLOW MODE 1.5 AVDD = DVDD NO LOAD 3.40 4.10 4.80 5.25 2.
Buffered, Fast-Settling, Octal, 12/10/8-Bit, Voltage-Output DACs MAX5590–MAX5595 Typical Operating Characteristics (continued) (AVDD = DVDD = 5V, VREF = 4.096V, RL = 10kΩ, CL = 100pF, speed mode = FAST, PU = unconnected, TA = +25°C, unless otherwise noted.
Buffered, Fast-Settling, Octal, 12/10/8-Bit, Voltage-Output DACs PIN MAX5590 MAX5592 MAX5594 MAX5591 MAX5593 MAX5595 1 1 AVDD 2 2 AGND Analog Ground 3 3 OUTA DACA Output 4, 8, 17, 21 — N.C. 5 6 OUTB DACB Output 6 7 OUTC DACC Output 7 10 OUTD 9 11 CS 10 12 SCLK Serial Clock Input 11 13 DIN Serial Data Input 12 14 DSP Clock Enable. Connect DSP to DVDD at power-up to transfer data on the rising edge of SCLK.
Buffered, Fast-Settling, Octal, 12/10/8-Bit, Voltage-Output DACs MAX5590–MAX5595 Functional Diagrams AVDD CS SCLK DIN DSP DVDD AGND DGND SERIAL INTERFACE CONTROL MAX5590 MAX5592 MAX5594 16-BIT SHIFT REGISTER MUX UPIO1 UPIO2 PU UPIO1 AND UPIO2 LOGIC DOUT REGISTER POWER-DOWN LOGIC AND REGISTER DECODE CONTROL OUTA INPUT REGISTER A DAC REGISTER A DACA INPUT REGISTER H DAC REGISTER H DACH OUTH REF 14 ______________________________________________________________________________________
Buffered, Fast-Settling, Octal, 12/10/8-Bit, Voltage-Output DACs AVDD CS SCLK DIN DSP DVDD AGND DGND SERIAL INTERFACE CONTROL MAX5591 MAX5593 MAX5595 16-BIT SHIFT REGISTER MUX UPIO1 UPIO2 PU UPIO1 AND UPIO2 LOGIC POWER-DOWN LOGIC AND REGISTER DOUT REGISTER FBA DECODE CONTROL OUTA INPUT REGISTER A DAC REGISTER A DACA FBH OUTH INPUT REGISTER H DAC REGISTER H DACH REF ______________________________________________________________________________________ 15 MAX5590–MAX5595 Functional
MAX5590–MAX5595 Buffered, Fast-Settling, Octal, 12/10/8-Bit, Voltage-Output DACs Detailed Description The MAX5590–MAX5595 octal, 12/10/8-bit, voltage-output DACs offer buffered outputs and a 3µs maximum settling time at the 12-bit level. The DACs operate from a single 2.7V to 5.25V analog supply and a separate 1.8V to AVDD digital supply. The MAX5590–MAX5595 include an input register and DAC register for each channel and a 16-bit data-in/data-out shift register.
Buffered, Fast-Settling, Octal, 12/10/8-Bit, Voltage-Output DACs MSB 16 BITS OF SERIAL DATA CONTROL BITS C3 C2 C1 LSB DATA BITS C0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 tCH SCLK tCL tDS DIN C3 tCS0 C2 C1 D0 tCSH tDH tCSS CS tCSW tCS1 tDO1 DOUTDC1* DOUT VALID tDO2 DOUTDC0 OR DOUTRB* DOUT VALID *UPIO1/UPIO2 CONFIGURED AS DOUTDC_ (DAISY-CHAIN DATA OUTPUT, MODE 0 OR 1) OR DOUTRB (READ-BACK DATA OUTPUT). SEE THE DATA OUTPUT (DOUTRB, DOUTDC0, DOUTDC1) SECTION FOR DETAILS. Figure 1.
MAX5590–MAX5595 Buffered, Fast-Settling, Octal, 12/10/8-Bit, Voltage-Output DACs Serial-Interface Programming Commands Loading Input and DAC Registers Tables 2a, 2b, and 2c provide all of the serial-interface programming commands for the MAX5590–MAX5595. Table 2a shows the basic DAC programming commands, Table 2b gives the advanced-feature programming commands, and Table 2c provides the 24-bit read commands. Figures 3 and 4 provide the serialinterface diagrams for read and write operations.
C3 C2 C1 ______________________________________________________________________________________ 0 0 0 0 0 0 0 DIN DIN DIN DIN DIN DIN DIN 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 D11 D10 D11 D10 D11 D10 D11 D10 D11 D10 D11 D10 D11 D10 D11 D10 D11 D10 D9 D9 D9 D9 D9 D9 D9 D9 D9 D8 D8 D8 D8 D8 D8 D8 D8 D8 D7 D7 D7 D7 D7 D7 D7 D7 D7 D6 D6 D6 D6 D6 D6 D6 D6 D6 D5 D5 D5 D5 D5 D5 D5 D5 D5 DATA BITS D3 D2 D1 D0
C3 1 0 C2 0 C1 CONTROL BITS 0 C0 X D11 1 DIN 0 0 1 DIN 0 ______________________________________________________________________________________ 0 1 X DIN DOUTRB X X 1 1 X 1 1 X 1 1 1 0 X 1 1 X 1 1 X 1 1 0 1 X 0 0 X 0 0 X 0 0 D11 D11 X 1 1 X 0 0 X 0 0 D10 D10 X 0 0 X 1 1 X 0 0 D9 D9 X D9 X 1 0 X 1 0 X 1 0 D8 D8 X D8 D6 D6 MG D6 D5 D5 MF D5 DATA BITS D4 D4 ME D4 D3/0 D3/0 MD D3 D2/0 D2/0 MC D
C2 C1 CONTROL BITS 0 1 X DIN DOUTRB X 1 1 0 1 X DIN DOUTRB X 1 1 X 1 1 X 1 1 C0 X 1 1 X 0 0 D11 X DOUTRB X 0 X 1 X 1 1 X DIN DOUTRB X = Don’t care.
CONTROL BITS X 1 X 1 X 1 X 1 X 1 X 1 X 1 X DOUTRB DIN DOUTRB DIN DOUTRB DIN DOUTRB DIN DOUTRB DIN DOUTRB DIN DOUTRB DIN DOUTRB X 1 X 1 X 1 X 1 X 1 X 1 X 1 X 1 X 0 X 0 X 0 X 0 X 0 X 0 X 0 X 0 X 1 X 1 X 1 X 1 X 1 X 1 X 1 X 1 X 1 X 1 X 1 X 1 X 0 X 0 X 0 X 0 X 1 X 1 X 0 X 0 X 1 X 1 X 0 X 0 X 1 X 0 X 1 X 0 X 1 X 0 X 1 X 0 X X X X X X X X X X X X X X X X 1 D23 1 1 1 1
Buffered, Fast-Settling, Octal, 12/10/8-Bit, Voltage-Output DACs Select Bits (M_) The select bits allow synchronous updating of any combination of channels. The select bits command the loading of the DAC register from the input register of each channel. Set the select bit M_ = 1 to load the DAC register “_” with data from the input register “_”, where “_” is replaced with A, B, or C and so on through H, depending on the selected channel.
MAX5590–MAX5595 Buffered, Fast-Settling, Octal, 12/10/8-Bit, Voltage-Output DACs Shutdown-Mode Bits (PD_0, PD_1) Use the shutdown-mode bits and control bits to shut down each DAC independently. The shutdownmode bits determine the output state of the selected channels. The shutdown-control bits put the selected channels into shutdown-mode. To select the shutdown mode for DACA–DACH, set PD_0 and PD_1 according to Table 8 (where “_” is replaced with one of the selected channels (A–H)).
Buffered, Fast-Settling, Octal, 12/10/8-Bit, Voltage-Output DACs CPOL and CPHA Control Bits The CPOL and CPHA control bits of the MAX5590–MAX5595 are defined the same as the CPOL and CPHA bits in the SPI standard. Set the DAC’s CPOL and CPHA bits to CPOL = 0 and CPHA = 0 or CPOL = 1 and CPHA = 1 for MICROWIRE and SPI applications requiring the clocking of data in on the ris- To read back the device’s CPOL and CPHA bits, use the command in Table 17. Table 13.
MAX5590–MAX5595 Buffered, Fast-Settling, Octal, 12/10/8-Bit, Voltage-Output DACs UPIO Bits (UPSL1, UPSL2, UP0–UP3) The MAX5590–MAX5595 provide two user-programmable input/output (UPIO) ports: UPIO1 and UPIO2. These ports have 15 possible configurations, as shown in Table 22. UPIO1 and UPIO2 can be programmed independently or simultaneously by writing to the UPSL1, UPSL2, and UP0–UP3 bits (Table 18). Table 19 shows how UPIO1 and UPIO2 are selected for configuration.
Buffered, Fast-Settling, Octal, 12/10/8-Bit, Voltage-Output DACs LDAC LDAC controls the loading of the DAC registers. When LDAC is high, the DAC registers are latched, and any change in the input registers does not affect the contents of the DAC registers or the DAC outputs. When LDAC is low, the DAC registers are transparent, and the values stored in the input registers are fed directly to the DAC registers, and the DAC outputs are updated.
MAX5590–MAX5595 Buffered, Fast-Settling, Octal, 12/10/8-Bit, Voltage-Output DACs tLDL LDAC END OF CYCLE* TOGG tGP PDL GPO_ tCMS CLR, MID, OR SET LDAC tS tLDS ±0.5 LSB VOUT_ PDL AFFECTS DAC OUPTUTS (VOUT_) ONLY IF DACS WERE PREVIOUSLY SHUT DOWN. * END-OF-CYCLE REPRESENTS THE RISING EDGE OF CS OR THE 16TH ACTIVE CLOCK EDGE, DEPENDING ON THE MODE OF OPERATION. Figure 5. Asynchronous Signal Timing Figure 6.
Buffered, Fast-Settling, Octal, 12/10/8-Bit, Voltage-Output DACs GPOL outputs a constant low, and GPOH outputs a constant high. See Figure 6. TOGG Use the TOGG input to toggle the DAC outputs between the values in the input registers and DAC registers. A delay of greater than 100ns from the end of the previous write command is required before the TOGG signal can be correctly switched between the new value and the previously stored value.
MAX5590–MAX5595 Buffered, Fast-Settling, Octal, 12/10/8-Bit, Voltage-Output DACs Applications Information Unipolar Output Figure 7 shows the unity-gain MAX5590 in a unipolar output configuration. Table 24 lists the unipolar output codes. 10kΩ 10kΩ V+ Bipolar Output The MAX5590 outputs can be configured for bipolar operation, as shown in Figure 8.
Buffered, Fast-Settling, Octal, 12/10/8-Bit, Voltage-Output DACs AVDD AVDD Using separate power supplies for AVDD and DVDD improves noise immunity. Connect AGND and DGND at the low-impedance power-supply sources (Figure 11). DVDD 0.1µF VREF inductance ground plane. Wire-wrapped boards and sockets are not recommended. For optimum system performance, use PC boards with separate analog and digital ground planes. Connect the two ground planes together at the low-impedance power-supply source. 10µF 0.
Buffered, Fast-Settling, Octal, 12/10/8-Bit, Voltage-Output DACs MAX5590–MAX5595 Pin Configurations TOP VIEW + AVDD 1 + 24 REF AGND 2 23 PU OUTA 3 22 OUTH N.C. 4 21 N.C. OUTB 5 OUTC 6 MAX5590 MAX5592 MAX5594 N.C. 8 17 N.C.
Buffered, Fast-Settling, Octal, 12/10/8-Bit, Voltage-Output DACs REVISION NUMBER REVISION DATE 2 7/07 3 1/10 DESCRIPTION Updated EC table specifications PAGES CHANGED 1, 6–9, 33 Added lead-free information and amended data sheet 1–13, 16, 20, 32, 33 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied.