Datasheet

MAX5703/MAX5704/MAX5705
Ultra-Small, Single-Channel, 8-/10-/12-Bit Buffered Output
Voltage DACs with Internal Reference and SPI Interface
16Maxim Integrated
CLR Mode
In CLR mode, the AUX input performs an asynchronous
level sensitive CLEAR operation when pulled low. If
CLR is configured and asserted, all CODE and DAC
data registers are cleared to their default/return values
as defined by the configuration settings. Other user-
configuration settings are not affected.
Some SPI interface commands are gated by CLR activity
during the transfer sequence. If CLR is issued during a
command write sequence, any gated commands within
the sequence are ignored. Any non-gated commands
appearing in the transfer sequence are executed. For
the gating condition to be removed, drive CLR high,
satisfying the t
CSC
requirements.
GATE Mode
Use of the GATE mode provides a means of momentarily
holding the DAC in a user-selectable default/return state,
returning the DAC to the last programmed state upon
removal. The MAX5703/MAX5704/MAX5705 also feature
a software-accessible GATE command. While asserted
in GATE mode, the AUX pin does not interfere with
RETURN, CODE, or DAC register updates and related
load activity.
LDAC Input
The MAX5703/MAX5704/MAX5705 provide a dedicated
asynchronous LDAC (active-low) input. The LDAC input
performs an asynchronous level sensitive LOAD operation
when pulled low. Use of the LDAC input mode provides
a means of updating multiple devices together as a
group. Users wishing to control the DAC update instance
independently of the I/O instruction should hold LDAC
high during programming cycles. Once programming
is complete, LDAC may be strobed and the new CODE
register content is loaded into the DAC latch output.
Users wishing to load new DAC data in direct response
to I/O CODE register activity should connect LDAC
permanently low; in this configuration, the MAX5703/
MAX5704/MAX5705 DAC output updates in response to
each completed I/O CODE instruction update edge. A
software LOAD command is also provided.
The LDAC operation does not interact with the user
interface directly. However, in order to achieve the best
possible glitch performance, timing with respect to the
interface update edge should follow t
LDH
specifications
when issuing CODE commands.
V
DDIO
Input
The MAX5703/MAX5704/MAX5705 feature a separate
supply pin (V
DDIO
) for the digital interface (1.8V to 5.5V).
Connect V
DDIO
to the I/O supply of the host processor.
SPI Serial Interface
The MAX5703/MAX5704/MAX5705 3-wire serial interface
is compatible with MICROWIRE/SPI/QSPI and DSPs. The
interface provides three inputs: SCLK, CS, and DIN. The
chip-select input (CS, active-low) frames the data loaded
through the serial data input (DIN). Following a CS input
high-to-low transition, the data is shifted in synchronously
and latched into the input register on each falling edge of
the serial clock input (SCLK). Each serial operation word
is 24-bits long. The DAC data is left justified as shown in
Table 1. The serial input register transfers its contents to
the destination registers after loading 24 bits of data on
the 24th SCLK falling edge. To initiate a new SPI opera-
tion, drive CS high and then low to begin the next opera-
tion sequence, being sure to meet all relevant timing
requirements. During CS high periods, SCLK is ignored,
allowing communication to other devices on the same
bus. SPI operations consisting of more than 24 SCLK
cycles are executed on the 24th SCLK falling edge, using
the first three bytes of data available. SPI operations con-
sisting of less than 24 SCLK cycles will not be executed.
The content of the SPI operation consists of a command
byte followed by a two byte data word.
Figure 1 shows the timing diagram for the complete
3-wire serial interface transmission. The DAC code
settings (D) for the MAX5703/MAX5704/MAX5705 are
accepted in an offset binary format (see Table 1).
Otherwise, the expected data format for each command
is listed in Table 2.
SPI User-Command Register Map
This section lists the user-accessible commands and
registers for the MAX5703/MAX5704/MAX5705.
Table 2 provides detailed information about the SPI
Command Registers.