Datasheet

MAX5703/MAX5704/MAX5705
Ultra-Small, Single-Channel, 8-/10-/12-Bit Buffered Output
Voltage DACs with Internal Reference and SPI Interface
7Maxim Integrated
ELECTRICAL CHARACTERISTICS (continued)
(V
DD
= 2.7V to 5.5V, V
DDIO
= 1.8V to 5.5V, V
GND
= 0V, C
L
= 200pF, R
L
= 2kI , T
A
= -40NC to +125NC, unless otherwise noted.)
(Note 2)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Hysteresis Voltage V
H
0.15 V
Input Leakage Current (Note 9) I
IN
±0.1 ±1 FA
Input Capacitance C
IN
3 pF
SPI TIMING CHARACTERISTICS (CS, SCLK, DIN, LDAC, AUX) (Note 10)
SCLK Frequency
2.7V ≤ V
DDIO
≤ 5.5V 0 50
MHz
1.8V ≤ V
DDIO
< 2.7V 0 33
SCLK Period
t
SCLK
2.7V ≤ V
DDIO
≤ 5.5V 20
ns
1.8V ≤ V
DDIO
< 2.7V 30
SCLK Pulse Width High
t
CH
8 ns
SCLK Pulse Width Low
t
CL
8 ns
CS Fall to SCLK Fall Setup Time
t
CSS0
To first SCLK
falling edge
2.7V ≤ V
DDIO
≤ 5.5V 8
ns
1.8V ≤ V
DDIO
< 2.7V 12
CS Fall to SCLK Fall Hold Time
t
CSH0
Applies to inactive SCLK falling edge
preceding the first SCLK falling edge
0 ns
CS Rise to SCLK Fall Hold Time
t
CSH1
Applies to the 24th SCLK falling edge 0 ns
CS Rise to SCLK Fall
t
CSA
Applies to the 24th SCLK falling edge,
aborted sequence
12 ns
SCLK Fall to CS Fall
t
CSF
Applies to 24th SCLK falling edge 100 ns
CS Pulse Width High
t
CSPW
20 ns
DIN to SCLK Fall Setup Time
t
DS
5 ns
DIN to SCLK Fall Hold Time
t
DH
4.5 ns
CLR Pulse Width Low
t
CLPW
20 ns
CLR Rise to CS Fall
t
CSC
Required for command to be executed 20 ns
LDAC Pulse Width Low
t
LDPW
20 ns
LDAC Fall to SCLK Fall Hold
t
LDH
Applies to 24th SCLK falling edge 20 ns