Datasheet

MAX5723/MAX5724/MAX5725
Ultra-Small, Octal-Channel, 8-/10-/12-Bit Buffered
Output DACs with Internal Reference and SPI Interface
7Maxim Integrated
ELECTRICAL CHARACTERISTICS (continued)
(V
DD
= 2.7V to 5.5V, V
DDIO
= 1.8V to 5.5V, V
GND
= 0V, C
L
= 200pF, R
L
= 2kI, T
A
= -40NC to +125NC, unless otherwise noted.)
(Note 3)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
SPI TIMING CHARACTERISTICS
SCLK Frequency
f
SCLK
2.7V < V
DDIO
< 5.5V
Write mode 0 50
MHz
Read mode,
strobing on 1 SCLK
0 25
Read mode,
strobing on ½ SCLK
0 12.5
1.8V < V
DDIO
< 2.7V
Write mode 0 33
Read mode,
strobing on 1 SCLK
0 20
Read mode,
strobing on ½ SCLK
0 10
SCLK Period
t
SCLK
2.7V < V
DDIO
< 5.5V, write mode 20
ns
1.8V < V
DDIO
< 2.7V, write mode 30
SCLK Pulse Width High
t
CH
8 ns
SCLK Pulse Width Low
t
CL
8 ns
CSB Fall to SCLK Fall Setup Time
t
CSS0
To first SCLK falling
edge
2
.7V < V
DDIO
< 5.5V 8
ns
1.8V < V
DDIO
< 2.7V 12
CSB Fall to SCLK Fall Hold Time
t
CSH0
Applies to inactive SCLK falling edge
preceding the first SCLK falling edge
0 ns
CSB Rise to SCLK Fall Hold Time
t
CSH1
Applies to the 24th SCLK falling edge 0 ns
CSB Rise to SCLK Fall
t
CSA
Applies to the 24th SCLK falling edge,
aborted sequence
12 ns
SCLK Fall to CSB Fall
t
CSF
Applies to 24th SCLK falling edge 100 ns
CSB Pulse Width High
t
CSPW
20 ns
DIN to SCLK Fall Setup Time
t
DS
5 ns
DIN to SCLK Fall Hold Time
t
DH
4.5 ns
CLR Pulse Width Low
t
CLPW
20 ns
CLR Rise to CSB Fall
t
CSC
Required for command to be executed 20 ns
LDAC Pulse Width Low
t
LDPW
20 ns
LDAC Fall to SCLK Fall Hold
t
LDH
Applies to 24th SCLK falling edge 20 ns
SCLK Fall to DOUT Transition
t
DOT
DPHA = 0,
C
LOAD
= 20pF
2.7V < V
DDIO
< 5.5V 35
ns
1.8V < V
DDIO
< 2.7V 40
SCLK Rise to DOUT Transition
t
DOT
DPHA = 1,
C
LOAD
= 20pF
2.7V < V
DDIO
< 5.5V 35
ns
1.8V < V
DDIO
< 2.7V 40