Datasheet

MAX5803/MAX5804/MAX5805
Ultra-Small, Single-Channel, 8-/10-/12-Bit Buffered Output
Voltage DACs with Internal Reference and I
2
C Interface
20Maxim Integrated
Figure 6. Standard I
2
C Register Read Sequence
Table 2. Standard I
2
C User Readback Data
Sample command sequences are shown in Figure 7. The
first command transfer is given in write mode with R/W =
0 and must be run to completion to qualify for interface
verification readback. There is now a STOP/START pair
or Repeated START condition required, followed by the
readback transfer with R/W = 1 to indicate a read and
an acknowledge clock from the MAX5803/MAX5804/
MAX5805. The master still has control of the SCL line but
the MAX5803/MAX5804/MAX5805 take over the SDA line.
The final three bytes in the frame contain the command
and register data written in the first transfer presented
for readback, followed by a STOP condition. If additional
bytes beyond those required to read back the requested
data are provided, the MAX5803/MAX5804/MAX5805 will
continue to read back ones.
It is not necessary for the write and read mode transfers
to occur immediately in sequence. I
2
C transfers involving
other devices do not impact the MAX5803/MAX5804/
MAX5805 readback mode. Toggling between readback
modes is based on the length of the preceding write
mode transfer. Combined format I
2
C readback operation
is resumed if a write command greater than two bytes
but less than four bytes is supplied. For commands writ-
ten using multiple register write sequences, only the last
command executed is read back. For each command
written, the readback sequence can only be completed
Table 3. DAC Data Bit Positions
COMMAND BYTE (REQUEST) READBACK DATA HIGH BYTE READBACK DATA LOW BYTE
B23 B22 B21 B20 B19 B18 B17 B16 B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
0 0 0 0 X X X X 0 1 0 1 0
REV_ID[2:0]
(000)
PART_ID[7:0]
MAX5803 = 0x8A
MAX5804 = 0x92
MAX5805 = 0x82
0 1 1 1 X X X X RETURN[11:4] RETURN[3:0] 0 0 0 0
1 0 0 0 X X X X CODE[11:4] CODE[3:0] 0 0 0 0
1 0 0 1 X X X X DAC[11:4] DAC[3:0] 0 0 0 0
1 0 1 0 X X X X DAC[11:4] DAC[3:0] 0 0 0 0
1 0 1 1 X X X X DAC[11:4] DAC[3:0] 0 0 0 0
Any other command CLR
LOAD
GATE
1 RF[3:0] PD[1:0] AB[2:0] DF[2:0]
PART B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
MAX5803 D7 D6 D5 D4 D3 D2 D1 D0 X X X X X X X X
MAX5804 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X X X X X
MAX5805 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X X X
READ DATA
BYTE #4: DATA1 HIGH
BYTE (B[15:8])
READ DATA
BYTE #5: DATA1
LOWBYTE (B[7:0])
REPEATED
START
READ ADDRESS
BYTE #3: I
2
C SLAVE
ADDRESS
WRITE ADDRESS
BYTE #1: I
2
C SLAVE
ADDRESS
WRITE COMMAND1
BYTE #2: COMMAND1
BYTE
ACK. GENERATED BY MAX5803/MAX5804/MAX5805 ACK. GENERATED BY I
2
C MASTERA
START STOP
SCL
SDA
0011 0A1A0W A
A
ANNN00110A1 A0 RADDDDDDDD DDDDDDDD
~A
ANNNNN