Datasheet

MAX5803/MAX5804/MAX5805
Ultra-Small, Single-Channel, 8-/10-/12-Bit Buffered Output
Voltage DACs with Internal Reference and I
2
C Interface
7Maxim Integrated
ELECTRICAL CHARACTERISTICS (continued)
(V
DD
= 2.7V to 5.5V, V
DDIO
= 1.8V to 5.5V, V
GND
= 0V, C
L
= 200pF, R
L
= 2kI , T
A
= -40NC to +125NC, unless otherwise noted.)
(Note 2)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Hysteresis Voltage V
H
0.15 V
Input Leakage Current (Note 9) I
IN
±0.1 ±1 FA
Input Capacitance C
IN
3 pF
ADDR Pullup/Pulldown Strength R
PU
, R
PD
(Note 10) 30 50 90 kI
DIGITAL OUTPUT (SDA)
Output Low Voltage V
OL
I
SINK
= 3mA 0.2 V
I
2
C TIMING CHARACTERISTICS (SCL, SDA, AUX, LDAC)
SCL Clock Frequency f
SCL
400 kHz
Bus Free Time Between a STOP
and a START Condition
t
BUF
1.3 µs
Hold Time Repeated for a START
Condition
t
HD;STA
0.6 µs
SCL Pulse Width Low t
LOW
1.3 µs
SCL Pulse Width High t
HIGH
0.6 µs
Setup Time for Repeated START
Condition
t
SU;STA
0.6 µs
Data Hold Time t
HD;DAT
0 900 ns
Data Setup Time t
SU;DAT
100 ns
SDA and SCL Receiving Rise
Time
t
R
20 +
C
B
/10
300 ns
SDA and SCL Receiving Fall
Time
t
F
20 +
C
B
/10
300 ns
SDA Transmitting Fall Time t
F
20 +
C
B
/10
250 ns
Setup Time for STOP Condition t
SU;STO
0.6 µs
Bus Capacitance Allowed C
B
V
DD
= 2.7V to 5.5V 10 400 pF
Pulse Width of Suppressed Spike t
SP
50 ns
CLR Removal Time Prior to a
Recognized START
t
CLRSTA
100 ns
CLR Pulse Width Low t
CLPW
20 ns
LDAC Pulse Width Low t
LDPW
20 ns
LDAC Fall to SCLK Fall to Hold t
LDH
Applies to execution edge 400 ns